740 lines
20 KiB
C
740 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Aquantia PHY drivers
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*
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Copyright 2018, 2021 NXP
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*/
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#include <config.h>
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <net.h>
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#include <phy.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <u-boot/crc.h>
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#include <malloc.h>
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#include <asm/byteorder.h>
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#include <fs.h>
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#define AQUNTIA_10G_CTL 0x20
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#define AQUNTIA_VENDOR_P1 0xc400
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#define AQUNTIA_SPEED_LSB_MASK 0x2000
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#define AQUNTIA_SPEED_MSB_MASK 0x40
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#define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812
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#define AQUANTIA_SYSTEM_INTERFACE_SR_READY BIT(0)
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#define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
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#define AQUANTIA_FIRMWARE_ID 0x20
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#define AQUANTIA_RESERVED_STATUS 0xc885
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#define AQUANTIA_FIRMWARE_MAJOR_MASK 0xff00
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#define AQUANTIA_FIRMWARE_MINOR_MASK 0xff
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#define AQUANTIA_FIRMWARE_BUILD_MASK 0xf0
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#define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
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#define AQUANTIA_SI_IN_USE_MASK 0x0078
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#define AQUANTIA_SI_USXGMII 0x0018
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/* registers in MDIO_MMD_VEND1 region */
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#define AQUANTIA_VND1_GLOBAL_SC 0x000
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#define AQUANTIA_VND1_GLOBAL_SC_LP BIT(0xb)
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#define GLOBAL_FIRMWARE_ID 0x20
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#define GLOBAL_FAULT 0xc850
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#define GLOBAL_RSTATUS_1 0xc885
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#define GLOBAL_ALARM_1 0xcc00
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#define SYSTEM_READY_BIT 0x40
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#define GLOBAL_STANDARD_CONTROL 0x0
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#define SOFT_RESET BIT(15)
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#define LOW_POWER BIT(11)
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#define MAILBOX_CONTROL 0x0200
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#define MAILBOX_EXECUTE BIT(15)
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#define MAILBOX_WRITE BIT(14)
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#define MAILBOX_RESET_CRC BIT(12)
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#define MAILBOX_BUSY BIT(8)
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#define MAILBOX_CRC 0x0201
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#define MAILBOX_ADDR_MSW 0x0202
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#define MAILBOX_ADDR_LSW 0x0203
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#define MAILBOX_DATA_MSW 0x0204
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#define MAILBOX_DATA_LSW 0x0205
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#define UP_CONTROL 0xc001
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#define UP_RESET BIT(15)
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#define UP_RUN_STALL_OVERRIDE BIT(6)
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#define UP_RUN_STALL BIT(0)
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#define AQUANTIA_PMA_RX_VENDOR_P1 0xe400
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#define AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK GENMASK(1, 0)
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/* MDI reversal configured through registers */
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#define AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG BIT(1)
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/* MDI reversal enabled */
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#define AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV BIT(0)
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/*
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* global start rate, the protocol associated with this speed is used by default
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* on SI.
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*/
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#define AQUANTIA_VND1_GSTART_RATE 0x31a
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#define AQUANTIA_VND1_GSTART_RATE_OFF 0
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#define AQUANTIA_VND1_GSTART_RATE_100M 1
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#define AQUANTIA_VND1_GSTART_RATE_1G 2
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#define AQUANTIA_VND1_GSTART_RATE_10G 3
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#define AQUANTIA_VND1_GSTART_RATE_2_5G 4
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#define AQUANTIA_VND1_GSTART_RATE_5G 5
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/* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */
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#define AQUANTIA_VND1_GSYSCFG_BASE 0x31b
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#define AQUANTIA_VND1_GSYSCFG_100M 0
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#define AQUANTIA_VND1_GSYSCFG_1G 1
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#define AQUANTIA_VND1_GSYSCFG_2_5G 2
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#define AQUANTIA_VND1_GSYSCFG_5G 3
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#define AQUANTIA_VND1_GSYSCFG_10G 4
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#define AQUANTIA_VND1_SMBUS0 0xc485
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#define AQUANTIA_VND1_SMBUS1 0xc495
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/* addresses of memory segments in the phy */
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#define DRAM_BASE_ADDR 0x3FFE0000
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#define IRAM_BASE_ADDR 0x40000000
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/* firmware image format constants */
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#define VERSION_STRING_SIZE 0x40
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#define VERSION_STRING_OFFSET 0x0200
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#define HEADER_OFFSET 0x300
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/* driver private data */
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#define AQUANTIA_NA 0
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#define AQUANTIA_GEN1 1
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#define AQUANTIA_GEN2 2
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#define AQUANTIA_GEN3 3
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#pragma pack(1)
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struct fw_header {
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u8 padding[4];
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u8 iram_offset[3];
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u8 iram_size[3];
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u8 dram_offset[3];
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u8 dram_size[3];
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};
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#pragma pack()
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#if defined(CONFIG_PHY_AQUANTIA_UPLOAD_FW)
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static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length)
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{
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loff_t length, read;
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int ret;
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void *addr = NULL;
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*fw_addr = NULL;
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*fw_length = 0;
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debug("Loading Acquantia microcode from %s %s\n",
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CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME);
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ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
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if (ret < 0)
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goto cleanup;
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ret = fs_size(CONFIG_PHY_AQUANTIA_FW_NAME, &length);
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if (ret < 0)
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goto cleanup;
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addr = malloc(length);
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if (!addr) {
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ret = -ENOMEM;
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goto cleanup;
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}
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ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
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if (ret < 0)
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goto cleanup;
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ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length,
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&read);
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if (ret < 0)
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goto cleanup;
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*fw_addr = addr;
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*fw_length = length;
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debug("Found Acquantia microcode.\n");
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cleanup:
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if (ret < 0) {
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printf("loading firmware file %s %s failed with error %d\n",
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CONFIG_PHY_AQUANTIA_FW_PART,
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CONFIG_PHY_AQUANTIA_FW_NAME, ret);
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free(addr);
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}
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return ret;
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}
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/* load data into the phy's memory */
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static int aquantia_load_memory(struct phy_device *phydev, u32 addr,
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const u8 *data, size_t len)
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{
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size_t pos;
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u16 crc = 0, up_crc;
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phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC);
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phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16);
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phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc);
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for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) {
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u32 word = 0;
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memcpy(&word, &data[pos], min(sizeof(u32), len - pos));
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phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW,
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(word >> 16));
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phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW,
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word & 0xffff);
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phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL,
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MAILBOX_EXECUTE | MAILBOX_WRITE);
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/* keep a big endian CRC to match the phy processor */
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word = cpu_to_be32(word);
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crc = crc16_ccitt(crc, (u8 *)&word, sizeof(word));
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}
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up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC);
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if (crc != up_crc) {
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printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n",
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phydev->dev->name, crc, up_crc);
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return -EINVAL;
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}
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return 0;
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}
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static u32 unpack_u24(const u8 *data)
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{
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return (data[2] << 16) + (data[1] << 8) + data[0];
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}
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static int aquantia_upload_firmware(struct phy_device *phydev)
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{
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int ret;
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u8 *addr = NULL;
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size_t fw_length = 0;
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u16 calculated_crc, read_crc;
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char version[VERSION_STRING_SIZE];
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u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size;
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const struct fw_header *header;
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ret = aquantia_read_fw(&addr, &fw_length);
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if (ret != 0)
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return ret;
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read_crc = (addr[fw_length - 2] << 8) | addr[fw_length - 1];
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calculated_crc = crc16_ccitt(0, addr, fw_length - 2);
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if (read_crc != calculated_crc) {
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printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n",
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phydev->dev->name, read_crc, calculated_crc);
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ret = -EINVAL;
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goto done;
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}
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/* Find the DRAM and IRAM sections within the firmware file. */
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primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12;
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header = (struct fw_header *)&addr[primary_offset + HEADER_OFFSET];
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iram_offset = primary_offset + unpack_u24(header->iram_offset);
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iram_size = unpack_u24(header->iram_size);
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dram_offset = primary_offset + unpack_u24(header->dram_offset);
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dram_size = unpack_u24(header->dram_size);
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debug("primary %d iram offset=%d size=%d dram offset=%d size=%d\n",
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primary_offset, iram_offset, iram_size, dram_offset, dram_size);
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strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET],
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VERSION_STRING_SIZE);
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printf("%s loading firmare version '%s'\n", phydev->dev->name, version);
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/* stall the microcprocessor */
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phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
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UP_RUN_STALL | UP_RUN_STALL_OVERRIDE);
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debug("loading dram 0x%08x from offset=%d size=%d\n",
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DRAM_BASE_ADDR, dram_offset, dram_size);
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ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset],
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dram_size);
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if (ret != 0)
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goto done;
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debug("loading iram 0x%08x from offset=%d size=%d\n",
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IRAM_BASE_ADDR, iram_offset, iram_size);
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ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset],
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iram_size);
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if (ret != 0)
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goto done;
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/* make sure soft reset and low power mode are clear */
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phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0);
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/* Release the microprocessor. UP_RESET must be held for 100 usec. */
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phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
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UP_RUN_STALL | UP_RUN_STALL_OVERRIDE | UP_RESET);
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udelay(100);
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phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE);
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printf("%s firmare loading done.\n", phydev->dev->name);
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done:
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free(addr);
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return ret;
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}
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#else
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static int aquantia_upload_firmware(struct phy_device *phydev)
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{
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printf("ERROR %s firmware loading disabled.\n", phydev->dev->name);
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return -1;
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}
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#endif
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struct {
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u16 syscfg;
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int cnt;
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u16 start_rate;
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} aquantia_syscfg[PHY_INTERFACE_MODE_MAX] = {
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[PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
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AQUANTIA_VND1_GSTART_RATE_1G},
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[PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
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AQUANTIA_VND1_GSTART_RATE_2_5G},
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[PHY_INTERFACE_MODE_10GBASER] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
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AQUANTIA_VND1_GSTART_RATE_10G},
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[PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G,
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AQUANTIA_VND1_GSTART_RATE_10G},
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};
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static int aquantia_set_proto(struct phy_device *phydev,
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phy_interface_t interface)
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{
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int i;
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if (!aquantia_syscfg[interface].cnt)
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return 0;
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/* set the default rate to enable the SI link */
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phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
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aquantia_syscfg[interface].start_rate);
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/* set selected protocol for all relevant line side link speeds */
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for (i = 0; i <= aquantia_syscfg[interface].cnt; i++)
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phy_write(phydev, MDIO_MMD_VEND1,
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AQUANTIA_VND1_GSYSCFG_BASE + i,
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aquantia_syscfg[interface].syscfg);
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return 0;
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}
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static int aquantia_dts_config(struct phy_device *phydev)
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{
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#ifdef CONFIG_DM_ETH
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ofnode node = phydev->node;
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u32 prop;
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u16 reg;
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/* this code only works on gen2 and gen3 PHYs */
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if (phydev->drv->data != AQUANTIA_GEN2 &&
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phydev->drv->data != AQUANTIA_GEN3)
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return -ENOTSUPP;
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if (!ofnode_valid(node))
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return 0;
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if (!ofnode_read_u32(node, "mdi-reversal", &prop)) {
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debug("mdi-reversal = %d\n", (int)prop);
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reg = phy_read(phydev, MDIO_MMD_PMAPMD,
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AQUANTIA_PMA_RX_VENDOR_P1);
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reg &= ~AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK;
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reg |= AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG;
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reg |= prop ? AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV : 0;
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phy_write(phydev, MDIO_MMD_PMAPMD, AQUANTIA_PMA_RX_VENDOR_P1,
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reg);
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}
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if (!ofnode_read_u32(node, "smb-addr", &prop)) {
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debug("smb-addr = %x\n", (int)prop);
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/*
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* there are two addresses here, normally just one bus would
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* be in use so we're setting both regs using the same DT
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* property.
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*/
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phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS0,
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(u16)(prop << 1));
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phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS1,
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(u16)(prop << 1));
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}
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#endif
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return 0;
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}
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static bool aquantia_link_is_up(struct phy_device *phydev)
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{
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u16 reg, regmask;
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int devad, regnum;
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/*
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* On Gen 2 and 3 we have a bit that indicates that both system and
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* line side are ready for data, use that if possible.
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*/
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if (phydev->drv->data == AQUANTIA_GEN2 ||
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phydev->drv->data == AQUANTIA_GEN3) {
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devad = MDIO_MMD_PHYXS;
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regnum = AQUANTIA_SYSTEM_INTERFACE_SR;
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regmask = AQUANTIA_SYSTEM_INTERFACE_SR_READY;
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} else {
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devad = MDIO_MMD_AN;
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regnum = MDIO_STAT1;
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regmask = MDIO_AN_STAT1_COMPLETE;
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}
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/* the register should be latched, do a double read */
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phy_read(phydev, devad, regnum);
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reg = phy_read(phydev, devad, regnum);
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return !!(reg & regmask);
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}
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int aquantia_config(struct phy_device *phydev)
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{
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int interface = phydev->interface;
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u32 val, id, rstatus, fault;
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u32 reg_val1 = 0;
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int num_retries = 5;
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int usx_an = 0;
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/*
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* check if the system is out of reset and init sequence completed.
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* chip-wide reset for gen1 quad phys takes longer
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*/
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while (--num_retries) {
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rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_ALARM_1);
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if (rstatus & SYSTEM_READY_BIT)
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break;
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mdelay(10);
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}
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id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
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rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
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fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT);
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if (id != 0)
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debug("%s running firmware version %X.%X.%X\n",
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phydev->dev->name, (id >> 8), id & 0xff,
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(rstatus >> 4) & 0xf);
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if (fault != 0)
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printf("%s fault 0x%04x detected\n", phydev->dev->name, fault);
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if (id == 0 || fault != 0) {
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int ret;
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ret = aquantia_upload_firmware(phydev);
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if (ret != 0)
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return ret;
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}
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/*
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* for backward compatibility convert XGMII into either 10GBase-R or
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* USXGMII based on FW config
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*/
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if (interface == PHY_INTERFACE_MODE_XGMII) {
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debug("use 10GBase-R or USXGMII SI protos, XGMII is not valid\n");
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reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
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AQUANTIA_SYSTEM_INTERFACE_SR);
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if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
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|
interface = PHY_INTERFACE_MODE_USXGMII;
|
|
else
|
|
interface = PHY_INTERFACE_MODE_10GBASER;
|
|
}
|
|
|
|
/*
|
|
* if link is up already we can just use it, otherwise configure
|
|
* the protocols in the PHY. If link is down set the system
|
|
* interface protocol to use based on phydev->interface
|
|
*/
|
|
if (!aquantia_link_is_up(phydev) &&
|
|
(phydev->drv->data == AQUANTIA_GEN2 ||
|
|
phydev->drv->data == AQUANTIA_GEN3)) {
|
|
/* set PHY in low power mode so we can configure protocols */
|
|
phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC,
|
|
AQUANTIA_VND1_GLOBAL_SC_LP);
|
|
mdelay(10);
|
|
|
|
/* configure protocol based on phydev->interface */
|
|
aquantia_set_proto(phydev, interface);
|
|
/* apply custom configuration based on DT */
|
|
aquantia_dts_config(phydev);
|
|
|
|
/* wake PHY back up */
|
|
phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
|
|
mdelay(10);
|
|
}
|
|
|
|
val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
|
|
|
|
switch (interface) {
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
/* 1000BASE-T mode */
|
|
phydev->advertising = SUPPORTED_1000baseT_Full;
|
|
phydev->supported = phydev->advertising;
|
|
|
|
val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
|
|
phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
|
|
break;
|
|
case PHY_INTERFACE_MODE_USXGMII:
|
|
usx_an = 1;
|
|
/* FALLTHROUGH */
|
|
case PHY_INTERFACE_MODE_10GBASER:
|
|
/* 10GBASE-T mode */
|
|
phydev->advertising = SUPPORTED_10000baseT_Full;
|
|
phydev->supported = phydev->advertising;
|
|
|
|
if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
|
|
!(val & AQUNTIA_SPEED_MSB_MASK))
|
|
phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
|
|
AQUNTIA_SPEED_LSB_MASK |
|
|
AQUNTIA_SPEED_MSB_MASK);
|
|
|
|
/* If SI is USXGMII then start USXGMII autoneg */
|
|
reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
|
|
AQUANTIA_VENDOR_PROVISIONING_REG);
|
|
|
|
if (usx_an) {
|
|
reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA;
|
|
debug("%s: system interface USXGMII\n",
|
|
phydev->dev->name);
|
|
} else {
|
|
reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA;
|
|
debug("%s: system interface 10GBase-R\n",
|
|
phydev->dev->name);
|
|
}
|
|
|
|
phy_write(phydev, MDIO_MMD_PHYXS,
|
|
AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1);
|
|
break;
|
|
case PHY_INTERFACE_MODE_2500BASEX:
|
|
/* 2.5GBASE-T mode */
|
|
phydev->advertising = SUPPORTED_1000baseT_Full;
|
|
phydev->supported = phydev->advertising;
|
|
|
|
phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
|
|
phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
|
|
break;
|
|
case PHY_INTERFACE_MODE_MII:
|
|
/* 100BASE-TX mode */
|
|
phydev->advertising = SUPPORTED_100baseT_Full;
|
|
phydev->supported = phydev->advertising;
|
|
|
|
val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
|
|
phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
|
|
break;
|
|
};
|
|
|
|
val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
|
|
reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
|
|
|
|
debug("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
|
|
phydev->drv->name,
|
|
(reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
|
|
reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
|
|
(val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int aquantia_startup(struct phy_device *phydev)
|
|
{
|
|
u32 speed;
|
|
int i = 0;
|
|
int reg;
|
|
|
|
phydev->duplex = DUPLEX_FULL;
|
|
|
|
/* if the AN is still in progress, wait till timeout. */
|
|
if (!aquantia_link_is_up(phydev)) {
|
|
printf("%s Waiting for PHY auto negotiation to complete",
|
|
phydev->dev->name);
|
|
do {
|
|
udelay(1000);
|
|
if ((i++ % 500) == 0)
|
|
printf(".");
|
|
} while (!aquantia_link_is_up(phydev) &&
|
|
i < (4 * PHY_ANEG_TIMEOUT));
|
|
|
|
if (i > PHY_ANEG_TIMEOUT)
|
|
printf(" TIMEOUT !\n");
|
|
}
|
|
|
|
/* Read twice because link state is latched and a
|
|
* read moves the current state into the register */
|
|
phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
|
|
reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
|
|
if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
|
|
phydev->link = 0;
|
|
else
|
|
phydev->link = 1;
|
|
|
|
speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
|
|
if (speed & AQUNTIA_SPEED_MSB_MASK) {
|
|
if (speed & AQUNTIA_SPEED_LSB_MASK)
|
|
phydev->speed = SPEED_10000;
|
|
else
|
|
phydev->speed = SPEED_1000;
|
|
} else {
|
|
if (speed & AQUNTIA_SPEED_LSB_MASK)
|
|
phydev->speed = SPEED_100;
|
|
else
|
|
phydev->speed = SPEED_10;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct phy_driver aq1202_driver = {
|
|
.name = "Aquantia AQ1202",
|
|
.uid = 0x3a1b445,
|
|
.mask = 0xfffffff0,
|
|
.features = PHY_10G_FEATURES,
|
|
.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
|
|
MDIO_MMD_PHYXS | MDIO_MMD_AN |
|
|
MDIO_MMD_VEND1),
|
|
.config = &aquantia_config,
|
|
.startup = &aquantia_startup,
|
|
.shutdown = &gen10g_shutdown,
|
|
};
|
|
|
|
struct phy_driver aq2104_driver = {
|
|
.name = "Aquantia AQ2104",
|
|
.uid = 0x3a1b460,
|
|
.mask = 0xfffffff0,
|
|
.features = PHY_10G_FEATURES,
|
|
.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
|
|
MDIO_MMD_PHYXS | MDIO_MMD_AN |
|
|
MDIO_MMD_VEND1),
|
|
.config = &aquantia_config,
|
|
.startup = &aquantia_startup,
|
|
.shutdown = &gen10g_shutdown,
|
|
};
|
|
|
|
struct phy_driver aqr105_driver = {
|
|
.name = "Aquantia AQR105",
|
|
.uid = 0x3a1b4a2,
|
|
.mask = 0xfffffff0,
|
|
.features = PHY_10G_FEATURES,
|
|
.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
|
|
MDIO_MMD_PHYXS | MDIO_MMD_AN |
|
|
MDIO_MMD_VEND1),
|
|
.config = &aquantia_config,
|
|
.startup = &aquantia_startup,
|
|
.shutdown = &gen10g_shutdown,
|
|
.data = AQUANTIA_GEN1,
|
|
};
|
|
|
|
struct phy_driver aqr106_driver = {
|
|
.name = "Aquantia AQR106",
|
|
.uid = 0x3a1b4d0,
|
|
.mask = 0xfffffff0,
|
|
.features = PHY_10G_FEATURES,
|
|
.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
|
|
MDIO_MMD_PHYXS | MDIO_MMD_AN |
|
|
MDIO_MMD_VEND1),
|
|
.config = &aquantia_config,
|
|
.startup = &aquantia_startup,
|
|
.shutdown = &gen10g_shutdown,
|
|
};
|
|
|
|
struct phy_driver aqr107_driver = {
|
|
.name = "Aquantia AQR107",
|
|
.uid = 0x3a1b4e0,
|
|
.mask = 0xfffffff0,
|
|
.features = PHY_10G_FEATURES,
|
|
.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
|
|
MDIO_MMD_PHYXS | MDIO_MMD_AN |
|
|
MDIO_MMD_VEND1),
|
|
.config = &aquantia_config,
|
|
.startup = &aquantia_startup,
|
|
.shutdown = &gen10g_shutdown,
|
|
.data = AQUANTIA_GEN2,
|
|
};
|
|
|
|
struct phy_driver aqr112_driver = {
|
|
.name = "Aquantia AQR112",
|
|
.uid = 0x3a1b660,
|
|
.mask = 0xfffffff0,
|
|
.features = PHY_10G_FEATURES,
|
|
.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
|
|
MDIO_MMD_PHYXS | MDIO_MMD_AN |
|
|
MDIO_MMD_VEND1),
|
|
.config = &aquantia_config,
|
|
.startup = &aquantia_startup,
|
|
.shutdown = &gen10g_shutdown,
|
|
.data = AQUANTIA_GEN3,
|
|
};
|
|
|
|
struct phy_driver aqr113c_driver = {
|
|
.name = "Aquantia AQR113C",
|
|
.uid = 0x31c31c12,
|
|
.mask = 0xfffffff0,
|
|
.features = PHY_10G_FEATURES,
|
|
.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
|
|
MDIO_MMD_PHYXS | MDIO_MMD_AN |
|
|
MDIO_MMD_VEND1),
|
|
.config = &aquantia_config,
|
|
.startup = &aquantia_startup,
|
|
.shutdown = &gen10g_shutdown,
|
|
.data = AQUANTIA_GEN3,
|
|
};
|
|
|
|
struct phy_driver aqr405_driver = {
|
|
.name = "Aquantia AQR405",
|
|
.uid = 0x3a1b4b2,
|
|
.mask = 0xfffffff0,
|
|
.features = PHY_10G_FEATURES,
|
|
.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
|
|
MDIO_MMD_PHYXS | MDIO_MMD_AN |
|
|
MDIO_MMD_VEND1),
|
|
.config = &aquantia_config,
|
|
.startup = &aquantia_startup,
|
|
.shutdown = &gen10g_shutdown,
|
|
.data = AQUANTIA_GEN1,
|
|
};
|
|
|
|
struct phy_driver aqr412_driver = {
|
|
.name = "Aquantia AQR412",
|
|
.uid = 0x3a1b710,
|
|
.mask = 0xfffffff0,
|
|
.features = PHY_10G_FEATURES,
|
|
.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
|
|
MDIO_MMD_PHYXS | MDIO_MMD_AN |
|
|
MDIO_MMD_VEND1),
|
|
.config = &aquantia_config,
|
|
.startup = &aquantia_startup,
|
|
.shutdown = &gen10g_shutdown,
|
|
.data = AQUANTIA_GEN3,
|
|
};
|
|
|
|
int phy_aquantia_init(void)
|
|
{
|
|
phy_register(&aq1202_driver);
|
|
phy_register(&aq2104_driver);
|
|
phy_register(&aqr105_driver);
|
|
phy_register(&aqr106_driver);
|
|
phy_register(&aqr107_driver);
|
|
phy_register(&aqr112_driver);
|
|
phy_register(&aqr113c_driver);
|
|
phy_register(&aqr405_driver);
|
|
phy_register(&aqr412_driver);
|
|
|
|
return 0;
|
|
}
|