286 lines
7.5 KiB
C
286 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 Mark Kettenis <kettenis@openbsd.org>
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* Copyright The Asahi Linux Contributors
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*/
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#include <common.h>
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#include <dm.h>
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#include <clk.h>
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#include <spi.h>
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#include <asm/io.h>
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#define APPLE_SPI_CTRL 0x000
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#define APPLE_SPI_CTRL_RUN BIT(0)
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#define APPLE_SPI_CTRL_TX_RESET BIT(2)
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#define APPLE_SPI_CTRL_RX_RESET BIT(3)
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#define APPLE_SPI_CFG 0x004
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#define APPLE_SPI_CFG_CPHA BIT(1)
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#define APPLE_SPI_CFG_CPOL BIT(2)
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#define APPLE_SPI_CFG_MODE GENMASK(6, 5)
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#define APPLE_SPI_CFG_MODE_POLLED 0
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#define APPLE_SPI_CFG_MODE_IRQ 1
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#define APPLE_SPI_CFG_MODE_DMA 2
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#define APPLE_SPI_CFG_IE_RXCOMPLETE BIT(7)
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#define APPLE_SPI_CFG_IE_TXRXTHRESH BIT(8)
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#define APPLE_SPI_CFG_LSB_FIRST BIT(13)
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#define APPLE_SPI_CFG_WORD_SIZE GENMASK(16, 15)
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#define APPLE_SPI_CFG_WORD_SIZE_8B 0
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#define APPLE_SPI_CFG_WORD_SIZE_16B 1
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#define APPLE_SPI_CFG_WORD_SIZE_32B 2
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#define APPLE_SPI_CFG_FIFO_THRESH GENMASK(18, 17)
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#define APPLE_SPI_CFG_FIFO_THRESH_8B 0
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#define APPLE_SPI_CFG_FIFO_THRESH_4B 1
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#define APPLE_SPI_CFG_FIFO_THRESH_1B 2
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#define APPLE_SPI_CFG_IE_TXCOMPLETE BIT(21)
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#define APPLE_SPI_STATUS 0x008
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#define APPLE_SPI_STATUS_RXCOMPLETE BIT(0)
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#define APPLE_SPI_STATUS_TXRXTHRESH BIT(1)
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#define APPLE_SPI_STATUS_TXCOMPLETE BIT(2)
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#define APPLE_SPI_PIN 0x00c
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#define APPLE_SPI_PIN_KEEP_MOSI BIT(0)
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#define APPLE_SPI_PIN_CS BIT(1)
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#define APPLE_SPI_TXDATA 0x010
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#define APPLE_SPI_RXDATA 0x020
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#define APPLE_SPI_CLKDIV 0x030
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#define APPLE_SPI_CLKDIV_MIN 0x002
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#define APPLE_SPI_CLKDIV_MAX 0x7ff
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#define APPLE_SPI_RXCNT 0x034
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#define APPLE_SPI_WORD_DELAY 0x038
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#define APPLE_SPI_TXCNT 0x04c
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#define APPLE_SPI_FIFOSTAT 0x10c
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#define APPLE_SPI_FIFOSTAT_TXFULL BIT(4)
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#define APPLE_SPI_FIFOSTAT_LEVEL_TX GENMASK(15, 8)
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#define APPLE_SPI_FIFOSTAT_RXEMPTY BIT(20)
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#define APPLE_SPI_FIFOSTAT_LEVEL_RX GENMASK(31, 24)
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#define APPLE_SPI_IE_XFER 0x130
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#define APPLE_SPI_IF_XFER 0x134
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#define APPLE_SPI_XFER_RXCOMPLETE BIT(0)
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#define APPLE_SPI_XFER_TXCOMPLETE BIT(1)
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#define APPLE_SPI_IE_FIFO 0x138
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#define APPLE_SPI_IF_FIFO 0x13c
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#define APPLE_SPI_FIFO_RXTHRESH BIT(4)
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#define APPLE_SPI_FIFO_TXTHRESH BIT(5)
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#define APPLE_SPI_FIFO_RXFULL BIT(8)
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#define APPLE_SPI_FIFO_TXEMPTY BIT(9)
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#define APPLE_SPI_FIFO_RXUNDERRUN BIT(16)
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#define APPLE_SPI_FIFO_TXOVERFLOW BIT(17)
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#define APPLE_SPI_SHIFTCFG 0x150
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#define APPLE_SPI_SHIFTCFG_CLK_ENABLE BIT(0)
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#define APPLE_SPI_SHIFTCFG_CS_ENABLE BIT(1)
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#define APPLE_SPI_SHIFTCFG_AND_CLK_DATA BIT(8)
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#define APPLE_SPI_SHIFTCFG_CS_AS_DATA BIT(9)
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#define APPLE_SPI_SHIFTCFG_TX_ENABLE BIT(10)
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#define APPLE_SPI_SHIFTCFG_RX_ENABLE BIT(11)
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#define APPLE_SPI_SHIFTCFG_BITS GENMASK(21, 16)
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#define APPLE_SPI_SHIFTCFG_OVERRIDE_CS BIT(24)
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#define APPLE_SPI_PINCFG 0x154
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#define APPLE_SPI_PINCFG_KEEP_CLK BIT(0)
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#define APPLE_SPI_PINCFG_KEEP_CS BIT(1)
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#define APPLE_SPI_PINCFG_KEEP_MOSI BIT(2)
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#define APPLE_SPI_PINCFG_CLK_IDLE_VAL BIT(8)
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#define APPLE_SPI_PINCFG_CS_IDLE_VAL BIT(9)
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#define APPLE_SPI_PINCFG_MOSI_IDLE_VAL BIT(10)
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#define APPLE_SPI_DELAY_PRE 0x160
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#define APPLE_SPI_DELAY_POST 0x168
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#define APPLE_SPI_DELAY_ENABLE BIT(0)
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#define APPLE_SPI_DELAY_NO_INTERBYTE BIT(1)
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#define APPLE_SPI_DELAY_SET_SCK BIT(4)
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#define APPLE_SPI_DELAY_SET_MOSI BIT(6)
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#define APPLE_SPI_DELAY_SCK_VAL BIT(8)
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#define APPLE_SPI_DELAY_MOSI_VAL BIT(12)
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#define APPLE_SPI_FIFO_DEPTH 16
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#define APPLE_SPI_TIMEOUT_MS 200
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struct apple_spi_priv {
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void *base;
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u32 clkfreq; /* Input clock frequency */
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};
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static void apple_spi_set_cs(struct apple_spi_priv *priv, int on)
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{
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writel(on ? 0 : APPLE_SPI_PIN_CS, priv->base + APPLE_SPI_PIN);
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}
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/* Fill Tx FIFO. */
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static void apple_spi_tx(struct apple_spi_priv *priv, uint *len,
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const void **dout)
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{
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const u8 *out = *dout;
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u32 data, fifostat;
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uint count;
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fifostat = readl(priv->base + APPLE_SPI_FIFOSTAT);
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count = APPLE_SPI_FIFO_DEPTH -
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FIELD_GET(APPLE_SPI_FIFOSTAT_LEVEL_TX, fifostat);
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while (*len > 0 && count > 0) {
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data = out ? *out++ : 0;
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writel(data, priv->base + APPLE_SPI_TXDATA);
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(*len)--;
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count--;
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}
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*dout = out;
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}
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/* Empty Rx FIFO. */
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static void apple_spi_rx(struct apple_spi_priv *priv, uint *len,
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void **din)
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{
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u8 *in = *din;
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u32 data, fifostat;
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uint count;
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fifostat = readl(priv->base + APPLE_SPI_FIFOSTAT);
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count = FIELD_GET(APPLE_SPI_FIFOSTAT_LEVEL_RX, fifostat);
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while (*len > 0 && count > 0) {
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data = readl(priv->base + APPLE_SPI_RXDATA);
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if (in)
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*in++ = data;
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(*len)--;
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count--;
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}
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*din = in;
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}
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static int apple_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct apple_spi_priv *priv = dev_get_priv(dev->parent);
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unsigned long start = get_timer(0);
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uint txlen, rxlen;
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int ret = 0;
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if ((bitlen % 8) != 0)
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return -EINVAL;
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txlen = rxlen = bitlen / 8;
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if (flags & SPI_XFER_BEGIN)
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apple_spi_set_cs(priv, 1);
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if (txlen > 0) {
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/* Reset FIFOs */
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writel(APPLE_SPI_CTRL_RX_RESET | APPLE_SPI_CTRL_TX_RESET,
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priv->base + APPLE_SPI_CTRL);
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/* Set the transfer length */
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writel(txlen, priv->base + APPLE_SPI_TXCNT);
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writel(rxlen, priv->base + APPLE_SPI_RXCNT);
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/* Prime transmit FIFO */
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apple_spi_tx(priv, &txlen, &dout);
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/* Start transfer */
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writel(APPLE_SPI_CTRL_RUN, priv->base + APPLE_SPI_CTRL);
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while ((txlen > 0 || rxlen > 0)) {
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apple_spi_rx(priv, &rxlen, &din);
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apple_spi_tx(priv, &txlen, &dout);
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if (get_timer(start) > APPLE_SPI_TIMEOUT_MS) {
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ret = -ETIMEDOUT;
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break;
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}
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}
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/* Stop transfer. */
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writel(0, priv->base + APPLE_SPI_CTRL);
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}
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if (flags & SPI_XFER_END)
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apple_spi_set_cs(priv, 0);
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return ret;
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}
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static int apple_spi_set_speed(struct udevice *dev, uint speed)
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{
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struct apple_spi_priv *priv = dev_get_priv(dev);
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u32 div;
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div = DIV_ROUND_UP(priv->clkfreq, speed);
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if (div < APPLE_SPI_CLKDIV_MIN)
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div = APPLE_SPI_CLKDIV_MIN;
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if (div > APPLE_SPI_CLKDIV_MAX)
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div = APPLE_SPI_CLKDIV_MAX;
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writel(div, priv->base + APPLE_SPI_CLKDIV);
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return 0;
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}
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static int apple_spi_set_mode(struct udevice *bus, uint mode)
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{
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return 0;
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}
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struct dm_spi_ops apple_spi_ops = {
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.xfer = apple_spi_xfer,
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.set_speed = apple_spi_set_speed,
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.set_mode = apple_spi_set_mode,
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};
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static int apple_spi_probe(struct udevice *dev)
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{
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struct apple_spi_priv *priv = dev_get_priv(dev);
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struct clk clkdev;
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int ret;
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priv->base = dev_read_addr_ptr(dev);
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if (!priv->base)
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return -EINVAL;
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ret = clk_get_by_index(dev, 0, &clkdev);
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if (ret)
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return ret;
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priv->clkfreq = clk_get_rate(&clkdev);
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/* Set CS high (inactive) and disable override and auto-CS */
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writel(APPLE_SPI_PIN_CS, priv->base + APPLE_SPI_PIN);
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writel(readl(priv->base + APPLE_SPI_SHIFTCFG) & ~APPLE_SPI_SHIFTCFG_OVERRIDE_CS,
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priv->base + APPLE_SPI_SHIFTCFG);
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writel((readl(priv->base + APPLE_SPI_PINCFG) & ~APPLE_SPI_PINCFG_CS_IDLE_VAL) |
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APPLE_SPI_PINCFG_KEEP_CS, priv->base + APPLE_SPI_PINCFG);
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/* Reset FIFOs */
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writel(APPLE_SPI_CTRL_RX_RESET | APPLE_SPI_CTRL_TX_RESET,
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priv->base + APPLE_SPI_CTRL);
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/* Configure defaults */
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writel(FIELD_PREP(APPLE_SPI_CFG_MODE, APPLE_SPI_CFG_MODE_IRQ) |
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FIELD_PREP(APPLE_SPI_CFG_WORD_SIZE, APPLE_SPI_CFG_WORD_SIZE_8B) |
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FIELD_PREP(APPLE_SPI_CFG_FIFO_THRESH, APPLE_SPI_CFG_FIFO_THRESH_8B),
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priv->base + APPLE_SPI_CFG);
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return 0;
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}
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static const struct udevice_id apple_spi_of_match[] = {
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{ .compatible = "apple,spi" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(apple_spi) = {
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.name = "apple_spi",
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.id = UCLASS_SPI,
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.of_match = apple_spi_of_match,
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.probe = apple_spi_probe,
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.priv_auto = sizeof(struct apple_spi_priv),
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.ops = &apple_spi_ops,
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};
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