516 lines
20 KiB
C
516 lines
20 KiB
C
/*
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* (C) Copyright 2006-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2006
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* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
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* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* sequoia.h - configuration for Sequoia & Rainier boards
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
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#ifndef CONFIG_RAINIER
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#define CONFIG_440EPX 1 /* Specific PPC440EPx */
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#define CONFIG_HOSTNAME sequoia
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#else
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#define CONFIG_440GRX 1 /* Specific PPC440GRx */
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#define CONFIG_HOSTNAME rainier
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#endif
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#define CONFIG_440 1 /* ... PPC440 family */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xFFF80000
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#endif
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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#include "amcc-common.h"
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/* Detect Sequoia PLL input clock automatically via CPLD bit */
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#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
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33333333 : 33000000)
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/*
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* Define this if you want support for video console with radeon 9200 pci card
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* Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
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*/
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#undef CONFIG_VIDEO
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#ifdef CONFIG_VIDEO
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/*
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* 44x dcache supported is working now on sequoia, but we don't enable
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* it yet since it needs further testing
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*/
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#define CONFIG_4xx_DCACHE /* enable dcache */
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#endif
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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/*
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* Base addresses -- Note these are effective addresses where the actual
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* resources get mapped (not physical addresses).
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*/
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#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0x0003
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#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
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#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
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#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
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#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
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#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
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#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
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#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
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#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
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#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
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#define CONFIG_SYS_USB2D0_BASE 0xe0000100
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#define CONFIG_SYS_USB_DEVICE 0xe0000000
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#define CONFIG_SYS_USB_HOST 0xe0000400
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#define CONFIG_SYS_BCSR_BASE 0xc0000000
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/*
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* Initial RAM & stack pointer
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*/
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/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
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#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
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/*
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* Environment
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*/
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#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
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#define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */
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#define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */
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#elif defined(CONFIG_SYS_RAMBOOT)
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#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */
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#define CONFIG_ENV_SIZE (8 << 10)
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/*
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* In RAM-booting version, we have no environment storage. So we need to
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* provide at least preliminary MAC addresses for the 4xx EMAC driver to
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* register the interfaces. Those two addresses are generated via the
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* tools/gen_eth_addr tool and should only be used in a closed laboratory
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* environment.
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*/
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#define CONFIG_ETHADDR 4a:56:49:22:3e:43
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#define CONFIG_ETH1ADDR 02:93:53:d5:06:98
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#else
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#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */
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#endif
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#if defined(CONFIG_CMD_FLASH)
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/*
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* FLASH related
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*/
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif
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#endif /* CONFIG_CMD_FLASH */
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/*
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* IPL (Initial Program Loader, integrated inside CPU)
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* Will load first 4k from NAND (SPL) into cache and execute it from there.
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*
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* SPL (Secondary Program Loader)
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* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
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* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
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* controller and the NAND controller so that the special U-Boot image can be
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* loaded from NAND to SDRAM.
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*
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* NUB (NAND U-Boot)
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* This NAND U-Boot (NUB) is a special U-Boot version which can be started
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* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
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*
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* On 440EPx the SPL is copied to SDRAM before the NAND controller is
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* set up. While still running from cache, I experienced problems accessing
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* the NAND controller. sr - 2006-08-25
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*/
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#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
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#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
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#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */
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/* this addr */
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#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
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/*
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* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
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*/
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
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/*
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* Now the NAND chip has to be defined (no autodetection used!)
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*/
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#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
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#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
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#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
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#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
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#define CONFIG_SYS_NAND_ECCSIZE 256
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
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#define CONFIG_SYS_NAND_OOBSIZE 16
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#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
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#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
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#ifdef CONFIG_ENV_IS_IN_NAND
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/*
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* For NAND booting the environment is embedded in the U-Boot image. Please take
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* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
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*/
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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#endif
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/*
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* DDR SDRAM
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*/
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#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
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!defined(CONFIG_SYS_RAMBOOT)
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#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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#endif
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#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
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/* 440EPx errata CHIP 11 */
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_MULTI_EEPROMS
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#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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/* I2C bootstrap EEPROM */
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
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#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
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/* I2C SYSMON (LM75, AD7414 is almost compatible) */
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#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
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#define CONFIG_DTT_AD7414 1 /* use AD7414 */
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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#define CONFIG_SYS_DTT_MAX_TEMP 70
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#define CONFIG_SYS_DTT_LOW_TEMP -30
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#define CONFIG_SYS_DTT_HYSTERESIS 3
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/*
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* Default environment variables
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_POWERPC \
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CONFIG_AMCC_DEF_ENV_PPC_OLD \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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CONFIG_AMCC_DEF_ENV_NAND_UPD \
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"kernel_addr=FC000000\0" \
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"ramdisk_addr=FC180000\0" \
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""
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#define CONFIG_M88E1111_PHY 1
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#define CONFIG_IBM_EMAC4_V4 1
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#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY1_ADDR 1
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/* USB */
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#ifdef CONFIG_440EPX
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#undef CONFIG_USB_EHCI /* OHCI by default */
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#ifdef CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_PPC4XX
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#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_EHCI_MMIO_BIG_ENDIAN
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#define CONFIG_EHCI_DESC_BIG_ENDIAN
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#ifdef CONFIG_4xx_DCACHE
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#define CONFIG_EHCI_DCACHE
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#endif
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#else /* CONFIG_USB_EHCI */
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_OHCI_BE_CONTROLLER
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#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
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#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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#endif
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#define CONFIG_USB_STORAGE
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/* Comment this out to enable USB 1.1 device */
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#define USB_2_0_DEVICE
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#endif /* CONFIG_440EPX */
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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/*
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* Commands additional to the ones defined in amcc-common.h
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*/
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#define CONFIG_CMD_CHIP_CONFIG
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#define CONFIG_CMD_DTT
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_SDRAM
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#ifdef CONFIG_440EPX
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#define CONFIG_CMD_USB
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#endif
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#ifndef CONFIG_RAINIER
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#define CONFIG_SYS_POST_FPU_ON CONFIG_SYS_POST_FPU
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#else
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#define CONFIG_SYS_POST_FPU_ON 0
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#endif
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/*
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* Don't run the memory POST on the NAND-booting version. It will
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* overwrite part of the U-Boot image which is already loaded from NAND
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* to SDRAM.
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*/
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#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
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#define CONFIG_SYS_POST_MEMORY_ON 0
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#else
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#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
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#endif
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/* POST support */
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#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
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CONFIG_SYS_POST_CPU | \
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CONFIG_SYS_POST_ETHER | \
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CONFIG_SYS_POST_FPU_ON | \
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CONFIG_SYS_POST_I2C | \
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CONFIG_SYS_POST_MEMORY_ON | \
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CONFIG_SYS_POST_SPR | \
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CONFIG_SYS_POST_UART)
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#define CONFIG_LOGBUFFER
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#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
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#define CONFIG_SUPPORT_VFAT
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/*
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* PCI stuff
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
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/* CONFIG_SYS_PCI_MEMBASE */
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/* Board-specific PCI */
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#define CONFIG_SYS_PCI_TARGET_INIT
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#define CONFIG_SYS_PCI_MASTER_INIT
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#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
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/*
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* External Bus Controller (EBC) Setup
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*/
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/*
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* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
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*/
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
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!defined(CONFIG_SYS_RAMBOOT)
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#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
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/* Memory Bank 0 (NOR-FLASH) initialization */
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#define CONFIG_SYS_EBC_PB0AP 0x03017200
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#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
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/* Memory Bank 3 (NAND-FLASH) initialization */
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#define CONFIG_SYS_EBC_PB3AP 0x018003c0
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#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
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#else
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#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
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/* Memory Bank 3 (NOR-FLASH) initialization */
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#define CONFIG_SYS_EBC_PB3AP 0x03017200
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#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH_BASE | 0xda000)
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/* Memory Bank 0 (NAND-FLASH) initialization */
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#define CONFIG_SYS_EBC_PB0AP 0x018003c0
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#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
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#endif
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/* Memory Bank 2 (CPLD) initialization */
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#define CONFIG_SYS_EBC_PB2AP 0x24814580
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#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x38000)
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#define CONFIG_SYS_BCSR5_PCI66EN 0x80
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/*
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* NAND FLASH
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*/
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
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#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
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/*
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* PPC440 GPIO Configuration
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*/
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/* test-only: take GPIO init from pcs440ep ???? in config file */
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#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
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{ \
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/* GPIO Core 0 */ \
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{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
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{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
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}, \
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{ \
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/* GPIO Core 1 */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
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|
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
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|
} \
|
|
}
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|
|
|
#ifdef CONFIG_VIDEO
|
|
#define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */
|
|
#define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
|
|
#define VIDEO_IO_OFFSET 0xe8000000
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|
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
|
|
#define CONFIG_VIDEO_SW_CURSOR
|
|
#define CONFIG_VIDEO_LOGO
|
|
#define CONFIG_CFB_CONSOLE
|
|
#define CONFIG_SPLASH_SCREEN
|
|
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
|
#define CONFIG_CMD_BMP
|
|
#endif
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|
|
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#endif /* __CONFIG_H */
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