1303 lines
34 KiB
Plaintext
1303 lines
34 KiB
Plaintext
/*
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* at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
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* applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
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* AT91SAM9X25, AT91SAM9X35 SoC
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*
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* Copyright (C) 2012 Atmel,
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* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
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*
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* Licensed under GPLv2 or later.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/at91.h>
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/ {
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model = "Atmel AT91SAM9x5 family SoC";
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compatible = "atmel,at91sam9x5";
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interrupt-parent = <&aic>;
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aliases {
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serial0 = &dbgu;
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serial1 = &usart0;
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serial2 = &usart1;
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serial3 = &usart2;
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gpio0 = &pioA;
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gpio1 = &pioB;
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gpio2 = &pioC;
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gpio3 = &pioD;
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tcb0 = &tcb0;
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tcb1 = &tcb1;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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ssc0 = &ssc0;
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pwm0 = &pwm0;
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spi0 = &spi0;
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};
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cpus {
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#address-cells = <0>;
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#size-cells = <0>;
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cpu {
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compatible = "arm,arm926ej-s";
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device_type = "cpu";
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};
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};
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memory {
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reg = <0x20000000 0x10000000>;
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};
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clocks {
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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adc_op_clk: adc_op_clk{
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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};
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};
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sram: sram@00300000 {
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compatible = "mmio-sram";
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reg = <0x00300000 0x8000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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u-boot,dm-pre-reloc;
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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u-boot,dm-pre-reloc;
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aic: interrupt-controller@fffff000 {
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#interrupt-cells = <3>;
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compatible = "atmel,at91rm9200-aic";
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interrupt-controller;
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reg = <0xfffff000 0x200>;
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atmel,external-irqs = <31>;
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};
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ramc0: ramc@ffffe800 {
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compatible = "atmel,at91sam9g45-ddramc";
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reg = <0xffffe800 0x200>;
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clocks = <&ddrck>;
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clock-names = "ddrck";
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};
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pmc: pmc@fffffc00 {
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compatible = "atmel,at91sam9x5-pmc", "syscon";
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reg = <0xfffffc00 0x200>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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u-boot,dm-pre-reloc;
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main_rc_osc: main_rc_osc {
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compatible = "atmel,at91sam9x5-clk-main-rc-osc";
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#clock-cells = <0>;
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interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
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clock-frequency = <12000000>;
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clock-accuracy = <50000000>;
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};
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main_osc: main_osc {
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compatible = "atmel,at91rm9200-clk-main-osc";
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#clock-cells = <0>;
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interrupts-extended = <&pmc AT91_PMC_MOSCS>;
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clocks = <&main_xtal>;
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};
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main: mainck {
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compatible = "atmel,at91sam9x5-clk-main";
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#clock-cells = <0>;
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interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
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clocks = <&main_rc_osc>, <&main_osc>;
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};
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plla: pllack@0 {
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compatible = "atmel,at91rm9200-clk-pll";
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#clock-cells = <0>;
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interrupts-extended = <&pmc AT91_PMC_LOCKA>;
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clocks = <&main>;
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reg = <0>;
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atmel,clk-input-range = <2000000 32000000>;
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#atmel,pll-clk-output-range-cells = <4>;
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atmel,pll-clk-output-ranges = <745000000 800000000 0 0
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695000000 750000000 1 0
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645000000 700000000 2 0
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595000000 650000000 3 0
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545000000 600000000 0 1
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495000000 555000000 1 1
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445000000 500000000 2 1
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400000000 450000000 3 1>;
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};
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plladiv: plladivck {
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compatible = "atmel,at91sam9x5-clk-plldiv";
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#clock-cells = <0>;
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clocks = <&plla>;
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};
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utmi: utmick {
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compatible = "atmel,at91sam9x5-clk-utmi";
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#clock-cells = <0>;
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interrupts-extended = <&pmc AT91_PMC_LOCKU>;
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clocks = <&main>;
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};
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mck: masterck {
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compatible = "atmel,at91sam9x5-clk-master";
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#clock-cells = <0>;
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interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
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clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
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atmel,clk-output-range = <0 133333333>;
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atmel,clk-divisors = <1 2 4 3>;
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atmel,master-clk-have-div3-pres;
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u-boot,dm-pre-reloc;
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};
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usb: usbck {
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compatible = "atmel,at91sam9x5-clk-usb";
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#clock-cells = <0>;
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clocks = <&plladiv>, <&utmi>;
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};
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prog: progck {
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compatible = "atmel,at91sam9x5-clk-programmable";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&pmc>;
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clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
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prog0: prog@0 {
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#clock-cells = <0>;
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reg = <0>;
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interrupts = <AT91_PMC_PCKRDY(0)>;
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};
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prog1: prog@1 {
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#clock-cells = <0>;
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reg = <1>;
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interrupts = <AT91_PMC_PCKRDY(1)>;
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};
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};
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smd: smdclk {
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compatible = "atmel,at91sam9x5-clk-smd";
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#clock-cells = <0>;
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clocks = <&plladiv>, <&utmi>;
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};
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systemck {
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compatible = "atmel,at91rm9200-clk-system";
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#address-cells = <1>;
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#size-cells = <0>;
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ddrck: ddrck@2 {
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#clock-cells = <0>;
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reg = <2>;
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clocks = <&mck>;
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};
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smdck: smdck@4 {
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#clock-cells = <0>;
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reg = <4>;
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clocks = <&smd>;
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};
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uhpck: uhpck@6 {
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#clock-cells = <0>;
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reg = <6>;
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clocks = <&usb>;
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};
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udpck: udpck@7 {
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#clock-cells = <0>;
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reg = <7>;
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clocks = <&usb>;
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};
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pck0: pck0@8 {
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#clock-cells = <0>;
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reg = <8>;
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clocks = <&prog0>;
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};
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pck1: pck1@9 {
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#clock-cells = <0>;
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reg = <9>;
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clocks = <&prog1>;
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};
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};
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periphck {
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compatible = "atmel,at91sam9x5-clk-peripheral";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mck>;
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u-boot,dm-pre-reloc;
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pioAB_clk: pioAB_clk@2 {
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#clock-cells = <0>;
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reg = <2>;
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};
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pioCD_clk: pioCD_clk@3 {
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#clock-cells = <0>;
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reg = <3>;
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};
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smd_clk: smd_clk@4 {
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#clock-cells = <0>;
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reg = <4>;
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};
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usart0_clk: usart0_clk@5 {
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#clock-cells = <0>;
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reg = <5>;
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};
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usart1_clk: usart1_clk@6 {
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#clock-cells = <0>;
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reg = <6>;
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};
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usart2_clk: usart2_clk@7 {
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#clock-cells = <0>;
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reg = <7>;
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};
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twi0_clk: twi0_clk@9 {
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reg = <9>;
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#clock-cells = <0>;
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};
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twi1_clk: twi1_clk@10 {
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#clock-cells = <0>;
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reg = <10>;
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};
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twi2_clk: twi2_clk@11 {
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#clock-cells = <0>;
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reg = <11>;
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};
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mci0_clk: mci0_clk@12 {
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#clock-cells = <0>;
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reg = <12>;
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};
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spi0_clk: spi0_clk@13 {
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#clock-cells = <0>;
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reg = <13>;
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};
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spi1_clk: spi1_clk@14 {
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#clock-cells = <0>;
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reg = <14>;
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};
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uart0_clk: uart0_clk@15 {
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#clock-cells = <0>;
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reg = <15>;
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};
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uart1_clk: uart1_clk@16 {
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#clock-cells = <0>;
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reg = <16>;
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};
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tcb0_clk: tcb0_clk@17 {
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#clock-cells = <0>;
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reg = <17>;
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};
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pwm_clk: pwm_clk@18 {
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#clock-cells = <0>;
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reg = <18>;
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};
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adc_clk: adc_clk@19 {
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#clock-cells = <0>;
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reg = <19>;
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};
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dma0_clk: dma0_clk@20 {
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#clock-cells = <0>;
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reg = <20>;
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};
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dma1_clk: dma1_clk@21 {
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#clock-cells = <0>;
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reg = <21>;
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};
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uhphs_clk: uhphs_clk@22 {
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#clock-cells = <0>;
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reg = <22>;
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};
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udphs_clk: udphs_clk@23 {
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#clock-cells = <0>;
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reg = <23>;
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};
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mci1_clk: mci1_clk@26 {
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#clock-cells = <0>;
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reg = <26>;
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};
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ssc0_clk: ssc0_clk@28 {
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#clock-cells = <0>;
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reg = <28>;
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};
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};
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};
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rstc@fffffe00 {
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compatible = "atmel,at91sam9g45-rstc";
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reg = <0xfffffe00 0x10>;
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clocks = <&clk32k>;
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};
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shdwc@fffffe10 {
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compatible = "atmel,at91sam9x5-shdwc";
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reg = <0xfffffe10 0x10>;
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clocks = <&clk32k>;
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};
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pit: timer@fffffe30 {
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compatible = "atmel,at91sam9260-pit";
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reg = <0xfffffe30 0xf>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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clocks = <&mck>;
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};
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sckc@fffffe50 {
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compatible = "atmel,at91sam9x5-sckc";
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reg = <0xfffffe50 0x4>;
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slow_osc: slow_osc {
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compatible = "atmel,at91sam9x5-clk-slow-osc";
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#clock-cells = <0>;
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clocks = <&slow_xtal>;
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};
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slow_rc_osc: slow_rc_osc {
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compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-accuracy = <50000000>;
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};
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clk32k: slck {
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compatible = "atmel,at91sam9x5-clk-slow";
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#clock-cells = <0>;
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clocks = <&slow_rc_osc>, <&slow_osc>;
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};
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};
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tcb0: timer@f8008000 {
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compatible = "atmel,at91sam9x5-tcb";
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reg = <0xf8008000 0x100>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&tcb0_clk>, <&clk32k>;
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clock-names = "t0_clk", "slow_clk";
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};
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tcb1: timer@f800c000 {
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compatible = "atmel,at91sam9x5-tcb";
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reg = <0xf800c000 0x100>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&tcb0_clk>, <&clk32k>;
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clock-names = "t0_clk", "slow_clk";
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};
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dma0: dma-controller@ffffec00 {
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compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffec00 0x200>;
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interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <2>;
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clocks = <&dma0_clk>;
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clock-names = "dma_clk";
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};
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dma1: dma-controller@ffffee00 {
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compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffee00 0x200>;
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interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <2>;
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clocks = <&dma1_clk>;
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clock-names = "dma_clk";
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};
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pinctrl@fffff400 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
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ranges = <0xfffff400 0xfffff400 0x800>;
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reg = <0xfffff400 0x200 /* pioA */
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0xfffff600 0x200 /* pioB */
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0xfffff800 0x200 /* pioC */
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0xfffffa00 0x200 /* pioD */
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>;
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u-boot,dm-pre-reloc;
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/* shared pinctrl settings */
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dbgu {
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u-boot,dm-pre-reloc;
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pinctrl_dbgu: dbgu-0 {
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atmel,pins =
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<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
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AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
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};
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};
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usart0 {
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pinctrl_usart0: usart0-0 {
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atmel,pins =
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<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */
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AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA1 periph A */
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};
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pinctrl_usart0_rts: usart0_rts-0 {
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atmel,pins =
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<AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
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};
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pinctrl_usart0_cts: usart0_cts-0 {
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atmel,pins =
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<AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
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};
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pinctrl_usart0_sck: usart0_sck-0 {
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atmel,pins =
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<AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */
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};
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};
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usart1 {
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pinctrl_usart1: usart1-0 {
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atmel,pins =
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<AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */
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AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */
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};
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pinctrl_usart1_rts: usart1_rts-0 {
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atmel,pins =
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<AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC27 periph C */
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};
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pinctrl_usart1_cts: usart1_cts-0 {
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atmel,pins =
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<AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C */
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};
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pinctrl_usart1_sck: usart1_sck-0 {
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atmel,pins =
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<AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */
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};
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};
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usart2 {
|
|
pinctrl_usart2: usart2-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
|
|
AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */
|
|
};
|
|
|
|
pinctrl_usart2_rts: usart2_rts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
|
|
};
|
|
|
|
pinctrl_usart2_cts: usart2_cts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
|
|
};
|
|
|
|
pinctrl_usart2_sck: usart2_sck-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
pinctrl_uart0: uart0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC8 periph C */
|
|
AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC9 periph C with pullup */
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
pinctrl_uart1: uart1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC16 periph C */
|
|
AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC17 periph C with pullup */
|
|
};
|
|
};
|
|
|
|
nand {
|
|
pinctrl_nand: nand-0 {
|
|
atmel,pins =
|
|
<AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */
|
|
AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A Write Enable */
|
|
AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A Address Latch Enable */
|
|
AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A Command Latch Enable */
|
|
AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD4 gpio Chip Enable pin pull_up */
|
|
AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY/BUSY pin pull_up */
|
|
AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */
|
|
AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A Data bit 1 */
|
|
AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A Data bit 2 */
|
|
AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A Data bit 3 */
|
|
AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A Data bit 4 */
|
|
AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A Data bit 5 */
|
|
AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD12 periph A Data bit 6 */
|
|
AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */
|
|
};
|
|
|
|
pinctrl_nand_16bits: nand_16bits-0 {
|
|
atmel,pins =
|
|
<AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A Data bit 8 */
|
|
AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A Data bit 9 */
|
|
AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD16 periph A Data bit 10 */
|
|
AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A Data bit 11 */
|
|
AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD18 periph A Data bit 12 */
|
|
AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD19 periph A Data bit 13 */
|
|
AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */
|
|
AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */
|
|
};
|
|
};
|
|
|
|
mmc0 {
|
|
pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
|
|
AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
|
|
AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
|
|
};
|
|
|
|
pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
|
|
AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
|
|
AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
|
|
};
|
|
};
|
|
|
|
mmc1 {
|
|
pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA13 periph B */
|
|
AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
|
|
AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA11 periph B with pullup */
|
|
};
|
|
|
|
pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA2 periph B with pullup */
|
|
AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA3 periph B with pullup */
|
|
AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA4 periph B with pullup */
|
|
};
|
|
};
|
|
|
|
ssc0 {
|
|
pinctrl_ssc0_tx: ssc0_tx-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
|
|
AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
|
|
AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
|
|
};
|
|
|
|
pinctrl_ssc0_rx: ssc0_rx-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
|
|
AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
|
|
AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
pinctrl_spi0: spi0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
|
|
AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
|
|
AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
|
|
};
|
|
};
|
|
|
|
spi1 {
|
|
pinctrl_spi1: spi1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
|
|
AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
|
|
AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
|
|
};
|
|
};
|
|
|
|
i2c0 {
|
|
pinctrl_i2c0: i2c0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A I2C0 data */
|
|
AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A I2C0 clock */
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
pinctrl_i2c1: i2c1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */
|
|
AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC1 periph C I2C1 clock */
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
pinctrl_i2c2: i2c2-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B I2C2 data */
|
|
AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B I2C2 clock */
|
|
};
|
|
};
|
|
|
|
i2c_gpio0 {
|
|
pinctrl_i2c_gpio0: i2c_gpio0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA30 gpio multidrive I2C0 data */
|
|
AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA31 gpio multidrive I2C0 clock */
|
|
};
|
|
};
|
|
|
|
i2c_gpio1 {
|
|
pinctrl_i2c_gpio1: i2c_gpio1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */
|
|
AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PC1 gpio multidrive I2C1 clock */
|
|
};
|
|
};
|
|
|
|
i2c_gpio2 {
|
|
pinctrl_i2c_gpio2: i2c_gpio2-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PB4 gpio multidrive I2C2 data */
|
|
AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB5 gpio multidrive I2C2 clock */
|
|
};
|
|
};
|
|
|
|
pwm0 {
|
|
pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 {
|
|
atmel,pins =
|
|
<AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 {
|
|
atmel,pins =
|
|
<AT91_PIOC 18 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 {
|
|
atmel,pins =
|
|
<AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 {
|
|
atmel,pins =
|
|
<AT91_PIOC 19 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 {
|
|
atmel,pins =
|
|
<AT91_PIOC 20 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
|
|
};
|
|
pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 {
|
|
atmel,pins =
|
|
<AT91_PIOC 21 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
|
|
tcb0 {
|
|
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
|
|
atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
|
|
atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
|
|
atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
|
|
atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
|
|
atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
|
|
atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
|
|
atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
|
|
atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
|
|
atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
|
|
tcb1 {
|
|
pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
|
|
atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
|
|
atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
|
|
atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
|
|
atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
|
|
atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
|
|
atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
|
|
atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
|
|
atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
|
|
atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pioA: gpio@fffff400 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff400 0x200>;
|
|
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioAB_clk>;
|
|
};
|
|
|
|
pioB: gpio@fffff600 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff600 0x200>;
|
|
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
#gpio-lines = <19>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioAB_clk>;
|
|
};
|
|
|
|
pioC: gpio@fffff800 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff800 0x200>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioCD_clk>;
|
|
};
|
|
|
|
pioD: gpio@fffffa00 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffffa00 0x200>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
#gpio-lines = <22>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioCD_clk>;
|
|
};
|
|
|
|
ssc0: ssc@f0010000 {
|
|
compatible = "atmel,at91sam9g45-ssc";
|
|
reg = <0xf0010000 0x4000>;
|
|
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>,
|
|
<&dma0 1 AT91_DMA_CFG_PER_ID(14)>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
|
|
clocks = <&ssc0_clk>;
|
|
clock-names = "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc0: mmc@f0008000 {
|
|
compatible = "atmel,hsmci";
|
|
reg = <0xf0008000 0x600>;
|
|
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
|
|
dma-names = "rxtx";
|
|
pinctrl-names = "default";
|
|
clocks = <&mci0_clk>;
|
|
clock-names = "mci_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc1: mmc@f000c000 {
|
|
compatible = "atmel,hsmci";
|
|
reg = <0xf000c000 0x600>;
|
|
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
|
|
dma-names = "rxtx";
|
|
pinctrl-names = "default";
|
|
clocks = <&mci1_clk>;
|
|
clock-names = "mci_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dbgu: serial@fffff200 {
|
|
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
|
|
reg = <0xfffff200 0x200>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_dbgu>;
|
|
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,
|
|
<&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&mck>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart0: serial@f801c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf801c000 0x200>;
|
|
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usart0>;
|
|
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>,
|
|
<&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&usart0_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart1: serial@f8020000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8020000 0x200>;
|
|
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usart1>;
|
|
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>,
|
|
<&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&usart1_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart2: serial@f8024000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8024000 0x200>;
|
|
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usart2>;
|
|
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>,
|
|
<&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&usart2_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@f8010000 {
|
|
compatible = "atmel,at91sam9x5-i2c";
|
|
reg = <0xf8010000 0x100>;
|
|
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
|
|
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>,
|
|
<&dma0 1 AT91_DMA_CFG_PER_ID(8)>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c0>;
|
|
clocks = <&twi0_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@f8014000 {
|
|
compatible = "atmel,at91sam9x5-i2c";
|
|
reg = <0xf8014000 0x100>;
|
|
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
|
|
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>,
|
|
<&dma1 1 AT91_DMA_CFG_PER_ID(6)>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
clocks = <&twi1_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@f8018000 {
|
|
compatible = "atmel,at91sam9x5-i2c";
|
|
reg = <0xf8018000 0x100>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
|
|
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>,
|
|
<&dma0 1 AT91_DMA_CFG_PER_ID(10)>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c2>;
|
|
clocks = <&twi2_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@f8040000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8040000 0x200>;
|
|
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart0>;
|
|
clocks = <&uart0_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@f8044000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8044000 0x200>;
|
|
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
clocks = <&uart1_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
adc0: adc@f804c000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "atmel,at91sam9x5-adc";
|
|
reg = <0xf804c000 0x100>;
|
|
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&adc_clk>,
|
|
<&adc_op_clk>;
|
|
clock-names = "adc_clk", "adc_op_clk";
|
|
atmel,adc-use-external-triggers;
|
|
atmel,adc-channels-used = <0xffff>;
|
|
atmel,adc-vref = <3300>;
|
|
atmel,adc-startup-time = <40>;
|
|
atmel,adc-sample-hold-time = <11>;
|
|
atmel,adc-res = <8 10>;
|
|
atmel,adc-res-names = "lowres", "highres";
|
|
atmel,adc-use-res = "highres";
|
|
|
|
trigger0 {
|
|
trigger-name = "external-rising";
|
|
trigger-value = <0x1>;
|
|
trigger-external;
|
|
};
|
|
|
|
trigger1 {
|
|
trigger-name = "external-falling";
|
|
trigger-value = <0x2>;
|
|
trigger-external;
|
|
};
|
|
|
|
trigger2 {
|
|
trigger-name = "external-any";
|
|
trigger-value = <0x3>;
|
|
trigger-external;
|
|
};
|
|
|
|
trigger3 {
|
|
trigger-name = "continuous";
|
|
trigger-value = <0x6>;
|
|
};
|
|
};
|
|
|
|
spi0: spi@f0000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xf0000000 0x100>;
|
|
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
|
|
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>,
|
|
<&dma0 1 AT91_DMA_CFG_PER_ID(2)>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi0>;
|
|
clocks = <&spi0_clk>;
|
|
clock-names = "spi_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@f0004000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xf0004000 0x100>;
|
|
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
|
|
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>,
|
|
<&dma1 1 AT91_DMA_CFG_PER_ID(2)>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi1>;
|
|
clocks = <&spi1_clk>;
|
|
clock-names = "spi_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2: gadget@f803c000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "atmel,at91sam9g45-udc";
|
|
reg = <0x00500000 0x80000
|
|
0xf803c000 0x400>;
|
|
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&utmi>, <&udphs_clk>;
|
|
clock-names = "hclk", "pclk";
|
|
status = "disabled";
|
|
|
|
ep@0 {
|
|
reg = <0>;
|
|
atmel,fifo-size = <64>;
|
|
atmel,nb-banks = <1>;
|
|
};
|
|
|
|
ep@1 {
|
|
reg = <1>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <2>;
|
|
atmel,can-dma;
|
|
atmel,can-isoc;
|
|
};
|
|
|
|
ep@2 {
|
|
reg = <2>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <2>;
|
|
atmel,can-dma;
|
|
atmel,can-isoc;
|
|
};
|
|
|
|
ep@3 {
|
|
reg = <3>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <3>;
|
|
atmel,can-dma;
|
|
};
|
|
|
|
ep@4 {
|
|
reg = <4>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <3>;
|
|
atmel,can-dma;
|
|
};
|
|
|
|
ep@5 {
|
|
reg = <5>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <3>;
|
|
atmel,can-dma;
|
|
atmel,can-isoc;
|
|
};
|
|
|
|
ep@6 {
|
|
reg = <6>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <3>;
|
|
atmel,can-dma;
|
|
atmel,can-isoc;
|
|
};
|
|
};
|
|
|
|
watchdog@fffffe40 {
|
|
compatible = "atmel,at91sam9260-wdt";
|
|
reg = <0xfffffe40 0x10>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&clk32k>;
|
|
atmel,watchdog-type = "hardware";
|
|
atmel,reset-type = "all";
|
|
atmel,dbg-halt;
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc@fffffeb0 {
|
|
compatible = "atmel,at91sam9x5-rtc";
|
|
reg = <0xfffffeb0 0x40>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&clk32k>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@f8034000 {
|
|
compatible = "atmel,at91sam9rl-pwm";
|
|
reg = <0xf8034000 0x300>;
|
|
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
|
|
clocks = <&pwm_clk>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
nand0: nand@40000000 {
|
|
compatible = "atmel,at91rm9200-nand";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x40000000 0x10000000
|
|
0xffffe000 0x600 /* PMECC Registers */
|
|
0xffffe600 0x200 /* PMECC Error Location Registers */
|
|
0x00108000 0x18000 /* PMECC looup table in ROM code */
|
|
>;
|
|
atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
|
|
atmel,nand-addr-offset = <21>;
|
|
atmel,nand-cmd-offset = <22>;
|
|
atmel,nand-has-dma;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_nand>;
|
|
gpios = <&pioD 5 GPIO_ACTIVE_HIGH
|
|
&pioD 4 GPIO_ACTIVE_HIGH
|
|
0
|
|
>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb0: ohci@00600000 {
|
|
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
|
|
reg = <0x00600000 0x100000>;
|
|
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
|
|
clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
|
|
clock-names = "ohci_clk", "hclk", "uhpck";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb1: ehci@00700000 {
|
|
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
|
|
reg = <0x00700000 0x100000>;
|
|
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
|
|
clocks = <&utmi>, <&uhphs_clk>;
|
|
clock-names = "usb_clk", "ehci_clk";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
i2c-gpio-0 {
|
|
compatible = "i2c-gpio";
|
|
gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
|
|
&pioA 31 GPIO_ACTIVE_HIGH /* scl */
|
|
>;
|
|
i2c-gpio,sda-open-drain;
|
|
i2c-gpio,scl-open-drain;
|
|
i2c-gpio,delay-us = <2>; /* ~100 kHz */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c_gpio0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c-gpio-1 {
|
|
compatible = "i2c-gpio";
|
|
gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
|
|
&pioC 1 GPIO_ACTIVE_HIGH /* scl */
|
|
>;
|
|
i2c-gpio,sda-open-drain;
|
|
i2c-gpio,scl-open-drain;
|
|
i2c-gpio,delay-us = <2>; /* ~100 kHz */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c_gpio1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c-gpio-2 {
|
|
compatible = "i2c-gpio";
|
|
gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
|
|
&pioB 5 GPIO_ACTIVE_HIGH /* scl */
|
|
>;
|
|
i2c-gpio,sda-open-drain;
|
|
i2c-gpio,scl-open-drain;
|
|
i2c-gpio,delay-us = <2>; /* ~100 kHz */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c_gpio2>;
|
|
status = "disabled";
|
|
};
|
|
};
|