117 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			117 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
| /*
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|  * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
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|  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| 
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| #include <common.h>
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| #include <dm.h>
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| #include <miiphy.h>
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| #include <asm/arch/stv0991_periph.h>
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| #include <asm/arch/stv0991_defs.h>
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| #include <asm/arch/hardware.h>
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| #include <asm/arch/gpio.h>
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| #include <netdev.h>
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| #include <asm/io.h>
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| #include <dm/platform_data/serial_pl01x.h>
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| 
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| DECLARE_GLOBAL_DATA_PTR;
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| 
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| struct gpio_regs *const gpioa_regs =
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| 		(struct gpio_regs *) GPIOA_BASE_ADDR;
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| 
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| #ifndef CONFIG_OF_CONTROL
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| static const struct pl01x_serial_platdata serial_platdata = {
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| 	.base = 0x80406000,
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| 	.type = TYPE_PL011,
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| 	.clock = 2700 * 1000,
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| };
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| 
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| U_BOOT_DEVICE(stv09911_serials) = {
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| 	.name = "serial_pl01x",
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| 	.platdata = &serial_platdata,
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| };
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| #endif
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| 
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| #ifdef CONFIG_SHOW_BOOT_PROGRESS
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| void show_boot_progress(int progress)
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| {
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| 	printf("%i\n", progress);
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| }
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| #endif
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| 
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| void enable_eth_phy(void)
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| {
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| 	/* Set GPIOA_06 pad HIGH (Appli board)*/
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| 	writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir);
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| 	writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data);
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| }
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| int board_eth_enable(void)
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| {
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| 	stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4);
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| 	clock_setup(ETH_CLOCK_CFG);
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| 	enable_eth_phy();
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| 	return 0;
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| }
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| 
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| int board_qspi_enable(void)
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| {
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| 	stv0991_pinmux_config(QSPI_CS_CLK_PAD);
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| 	clock_setup(QSPI_CLOCK_CFG);
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| 	return 0;
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| }
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| 
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| /*
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|  * Miscellaneous platform dependent initialisations
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|  */
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| int board_init(void)
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| {
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| 	board_eth_enable();
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| 	board_qspi_enable();
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| 	return 0;
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| }
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| 
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| int board_uart_init(void)
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| {
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| 	stv0991_pinmux_config(UART_GPIOC_30_31);
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| 	clock_setup(UART_CLOCK_CFG);
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| 	return 0;
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| }
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| 
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| #ifdef CONFIG_BOARD_EARLY_INIT_F
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| int board_early_init_f(void)
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| {
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| 	board_uart_init();
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| 	return 0;
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| }
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| #endif
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| 
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| int dram_init(void)
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| {
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| 	gd->ram_size = PHYS_SDRAM_1_SIZE;
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| 	return 0;
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| }
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| 
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| int dram_init_banksize(void)
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| {
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| 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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| 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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| 
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| 	return 0;
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| }
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| 
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| #ifdef CONFIG_CMD_NET
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| int board_eth_init(bd_t *bis)
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| {
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| 	int ret = 0;
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| 
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| #if defined(CONFIG_ETH_DESIGNWARE)
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| 	u32 interface = PHY_INTERFACE_MODE_MII;
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| 	if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0)
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| 		ret++;
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| #endif
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| 	return ret;
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| }
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| #endif
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