497 lines
14 KiB
C
497 lines
14 KiB
C
/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
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*/
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#include <common.h>
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#include <clk.h>
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#include <ram.h>
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#include <reset.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <linux/iopoll.h>
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#include "stm32mp1_ddr.h"
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#include "stm32mp1_ddr_regs.h"
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#define RCC_DDRITFCR 0xD8
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#define RCC_DDRITFCR_DDRCAPBRST (BIT(14))
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#define RCC_DDRITFCR_DDRCAXIRST (BIT(15))
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#define RCC_DDRITFCR_DDRCORERST (BIT(16))
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#define RCC_DDRITFCR_DPHYAPBRST (BIT(17))
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#define RCC_DDRITFCR_DPHYRST (BIT(18))
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#define RCC_DDRITFCR_DPHYCTLRST (BIT(19))
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struct reg_desc {
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const char *name;
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u16 offset; /* offset for base address */
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u8 par_offset; /* offset for parameter array */
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};
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#define INVALID_OFFSET 0xFF
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#define DDRCTL_REG(x, y) \
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{#x,\
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offsetof(struct stm32mp1_ddrctl, x),\
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offsetof(struct y, x)}
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#define DDRPHY_REG(x, y) \
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{#x,\
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offsetof(struct stm32mp1_ddrphy, x),\
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offsetof(struct y, x)}
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#define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
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static const struct reg_desc ddr_reg[] = {
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DDRCTL_REG_REG(mstr),
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DDRCTL_REG_REG(mrctrl0),
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DDRCTL_REG_REG(mrctrl1),
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DDRCTL_REG_REG(derateen),
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DDRCTL_REG_REG(derateint),
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DDRCTL_REG_REG(pwrctl),
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DDRCTL_REG_REG(pwrtmg),
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DDRCTL_REG_REG(hwlpctl),
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DDRCTL_REG_REG(rfshctl0),
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DDRCTL_REG_REG(rfshctl3),
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DDRCTL_REG_REG(crcparctl0),
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DDRCTL_REG_REG(zqctl0),
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DDRCTL_REG_REG(dfitmg0),
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DDRCTL_REG_REG(dfitmg1),
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DDRCTL_REG_REG(dfilpcfg0),
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DDRCTL_REG_REG(dfiupd0),
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DDRCTL_REG_REG(dfiupd1),
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DDRCTL_REG_REG(dfiupd2),
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DDRCTL_REG_REG(dfiphymstr),
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DDRCTL_REG_REG(odtmap),
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DDRCTL_REG_REG(dbg0),
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DDRCTL_REG_REG(dbg1),
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DDRCTL_REG_REG(dbgcmd),
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DDRCTL_REG_REG(poisoncfg),
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DDRCTL_REG_REG(pccfg),
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};
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#define DDRCTL_REG_TIMING(x) DDRCTL_REG(x, stm32mp1_ddrctrl_timing)
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static const struct reg_desc ddr_timing[] = {
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DDRCTL_REG_TIMING(rfshtmg),
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DDRCTL_REG_TIMING(dramtmg0),
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DDRCTL_REG_TIMING(dramtmg1),
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DDRCTL_REG_TIMING(dramtmg2),
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DDRCTL_REG_TIMING(dramtmg3),
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DDRCTL_REG_TIMING(dramtmg4),
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DDRCTL_REG_TIMING(dramtmg5),
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DDRCTL_REG_TIMING(dramtmg6),
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DDRCTL_REG_TIMING(dramtmg7),
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DDRCTL_REG_TIMING(dramtmg8),
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DDRCTL_REG_TIMING(dramtmg14),
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DDRCTL_REG_TIMING(odtcfg),
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};
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#define DDRCTL_REG_MAP(x) DDRCTL_REG(x, stm32mp1_ddrctrl_map)
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static const struct reg_desc ddr_map[] = {
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DDRCTL_REG_MAP(addrmap1),
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DDRCTL_REG_MAP(addrmap2),
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DDRCTL_REG_MAP(addrmap3),
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DDRCTL_REG_MAP(addrmap4),
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DDRCTL_REG_MAP(addrmap5),
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DDRCTL_REG_MAP(addrmap6),
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DDRCTL_REG_MAP(addrmap9),
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DDRCTL_REG_MAP(addrmap10),
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DDRCTL_REG_MAP(addrmap11),
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};
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#define DDRCTL_REG_PERF(x) DDRCTL_REG(x, stm32mp1_ddrctrl_perf)
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static const struct reg_desc ddr_perf[] = {
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DDRCTL_REG_PERF(sched),
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DDRCTL_REG_PERF(sched1),
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DDRCTL_REG_PERF(perfhpr1),
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DDRCTL_REG_PERF(perflpr1),
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DDRCTL_REG_PERF(perfwr1),
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DDRCTL_REG_PERF(pcfgr_0),
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DDRCTL_REG_PERF(pcfgw_0),
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DDRCTL_REG_PERF(pcfgqos0_0),
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DDRCTL_REG_PERF(pcfgqos1_0),
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DDRCTL_REG_PERF(pcfgwqos0_0),
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DDRCTL_REG_PERF(pcfgwqos1_0),
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DDRCTL_REG_PERF(pcfgr_1),
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DDRCTL_REG_PERF(pcfgw_1),
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DDRCTL_REG_PERF(pcfgqos0_1),
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DDRCTL_REG_PERF(pcfgqos1_1),
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DDRCTL_REG_PERF(pcfgwqos0_1),
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DDRCTL_REG_PERF(pcfgwqos1_1),
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};
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#define DDRPHY_REG_REG(x) DDRPHY_REG(x, stm32mp1_ddrphy_reg)
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static const struct reg_desc ddrphy_reg[] = {
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DDRPHY_REG_REG(pgcr),
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DDRPHY_REG_REG(aciocr),
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DDRPHY_REG_REG(dxccr),
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DDRPHY_REG_REG(dsgcr),
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DDRPHY_REG_REG(dcr),
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DDRPHY_REG_REG(odtcr),
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DDRPHY_REG_REG(zq0cr1),
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DDRPHY_REG_REG(dx0gcr),
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DDRPHY_REG_REG(dx1gcr),
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DDRPHY_REG_REG(dx2gcr),
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DDRPHY_REG_REG(dx3gcr),
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};
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#define DDRPHY_REG_TIMING(x) DDRPHY_REG(x, stm32mp1_ddrphy_timing)
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static const struct reg_desc ddrphy_timing[] = {
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DDRPHY_REG_TIMING(ptr0),
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DDRPHY_REG_TIMING(ptr1),
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DDRPHY_REG_TIMING(ptr2),
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DDRPHY_REG_TIMING(dtpr0),
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DDRPHY_REG_TIMING(dtpr1),
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DDRPHY_REG_TIMING(dtpr2),
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DDRPHY_REG_TIMING(mr0),
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DDRPHY_REG_TIMING(mr1),
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DDRPHY_REG_TIMING(mr2),
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DDRPHY_REG_TIMING(mr3),
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};
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#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
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static const struct reg_desc ddrphy_cal[] = {
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DDRPHY_REG_CAL(dx0dllcr),
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DDRPHY_REG_CAL(dx0dqtr),
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DDRPHY_REG_CAL(dx0dqstr),
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DDRPHY_REG_CAL(dx1dllcr),
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DDRPHY_REG_CAL(dx1dqtr),
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DDRPHY_REG_CAL(dx1dqstr),
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DDRPHY_REG_CAL(dx2dllcr),
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DDRPHY_REG_CAL(dx2dqtr),
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DDRPHY_REG_CAL(dx2dqstr),
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DDRPHY_REG_CAL(dx3dllcr),
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DDRPHY_REG_CAL(dx3dqtr),
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DDRPHY_REG_CAL(dx3dqstr),
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};
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enum reg_type {
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REG_REG,
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REG_TIMING,
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REG_PERF,
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REG_MAP,
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REGPHY_REG,
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REGPHY_TIMING,
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REGPHY_CAL,
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REG_TYPE_NB
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};
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enum base_type {
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DDR_BASE,
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DDRPHY_BASE,
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NONE_BASE
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};
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struct ddr_reg_info {
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const char *name;
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const struct reg_desc *desc;
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u8 size;
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enum base_type base;
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};
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#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
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const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
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[REG_REG] = {
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"static", ddr_reg, ARRAY_SIZE(ddr_reg), DDR_BASE},
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[REG_TIMING] = {
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"timing", ddr_timing, ARRAY_SIZE(ddr_timing), DDR_BASE},
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[REG_PERF] = {
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"perf", ddr_perf, ARRAY_SIZE(ddr_perf), DDR_BASE},
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[REG_MAP] = {
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"map", ddr_map, ARRAY_SIZE(ddr_map), DDR_BASE},
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[REGPHY_REG] = {
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"static", ddrphy_reg, ARRAY_SIZE(ddrphy_reg), DDRPHY_BASE},
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[REGPHY_TIMING] = {
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"timing", ddrphy_timing, ARRAY_SIZE(ddrphy_timing), DDRPHY_BASE},
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[REGPHY_CAL] = {
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"cal", ddrphy_cal, ARRAY_SIZE(ddrphy_cal), DDRPHY_BASE},
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};
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const char *base_name[] = {
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[DDR_BASE] = "ctl",
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[DDRPHY_BASE] = "phy",
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};
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static u32 get_base_addr(const struct ddr_info *priv, enum base_type base)
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{
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if (base == DDRPHY_BASE)
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return (u32)priv->phy;
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else
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return (u32)priv->ctl;
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}
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static void set_reg(const struct ddr_info *priv,
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enum reg_type type,
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const void *param)
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{
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unsigned int i;
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unsigned int *ptr, value;
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enum base_type base = ddr_registers[type].base;
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u32 base_addr = get_base_addr(priv, base);
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const struct reg_desc *desc = ddr_registers[type].desc;
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debug("init %s\n", ddr_registers[type].name);
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for (i = 0; i < ddr_registers[type].size; i++) {
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ptr = (unsigned int *)(base_addr + desc[i].offset);
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if (desc[i].par_offset == INVALID_OFFSET) {
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pr_err("invalid parameter offset for %s", desc[i].name);
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} else {
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value = *((u32 *)((u32)param +
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desc[i].par_offset));
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writel(value, ptr);
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debug("[0x%x] %s= 0x%08x\n",
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(u32)ptr, desc[i].name, value);
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}
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}
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}
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static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
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{
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u32 pgsr;
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int ret;
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ret = readl_poll_timeout(&phy->pgsr, pgsr,
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pgsr & (DDRPHYC_PGSR_IDONE |
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DDRPHYC_PGSR_DTERR |
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DDRPHYC_PGSR_DTIERR |
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DDRPHYC_PGSR_DFTERR |
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DDRPHYC_PGSR_RVERR |
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DDRPHYC_PGSR_RVEIRR),
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1000000);
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debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
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(u32)&phy->pgsr, pgsr, ret);
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}
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void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
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{
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pir |= DDRPHYC_PIR_INIT;
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writel(pir, &phy->pir);
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debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
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(u32)&phy->pir, pir, readl(&phy->pir));
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/* need to wait 10 configuration clock before start polling */
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udelay(10);
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/* Wait DRAM initialization and Gate Training Evaluation complete */
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ddrphy_idone_wait(phy);
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}
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/* start quasi dynamic register update */
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static void start_sw_done(struct stm32mp1_ddrctl *ctl)
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{
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clrbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
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}
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/* wait quasi dynamic register update */
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static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
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{
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int ret;
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u32 swstat;
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setbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
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ret = readl_poll_timeout(&ctl->swstat, swstat,
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swstat & DDRCTRL_SWSTAT_SW_DONE_ACK,
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1000000);
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if (ret)
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panic("Timeout initialising DRAM : DDR->swstat = %x\n",
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swstat);
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debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
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}
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/* wait quasi dynamic register update */
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static void wait_operating_mode(struct ddr_info *priv, int mode)
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{
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u32 stat, val, mask, val2 = 0, mask2 = 0;
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int ret;
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mask = DDRCTRL_STAT_OPERATING_MODE_MASK;
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val = mode;
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/* self-refresh due to software => check also STAT.selfref_type */
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if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) {
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mask |= DDRCTRL_STAT_SELFREF_TYPE_MASK;
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stat |= DDRCTRL_STAT_SELFREF_TYPE_SR;
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} else if (mode == DDRCTRL_STAT_OPERATING_MODE_NORMAL) {
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/* normal mode: handle also automatic self refresh */
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mask2 = DDRCTRL_STAT_OPERATING_MODE_MASK |
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DDRCTRL_STAT_SELFREF_TYPE_MASK;
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val2 = DDRCTRL_STAT_OPERATING_MODE_SR |
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DDRCTRL_STAT_SELFREF_TYPE_ASR;
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}
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ret = readl_poll_timeout(&priv->ctl->stat, stat,
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((stat & mask) == val) ||
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(mask2 && ((stat & mask2) == val2)),
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1000000);
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if (ret)
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panic("Timeout DRAM : DDR->stat = %x\n", stat);
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debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
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}
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void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
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{
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start_sw_done(ctl);
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/* quasi-dynamic register update*/
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setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
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clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
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clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
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wait_sw_done_ack(ctl);
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}
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void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
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u32 rfshctl3, u32 pwrctl)
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{
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start_sw_done(ctl);
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if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH))
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clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
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if (pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN)
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setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
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setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
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wait_sw_done_ack(ctl);
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}
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/* board-specific DDR power initializations. */
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__weak int board_ddr_power_init(void)
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{
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return 0;
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}
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__maybe_unused
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void stm32mp1_ddr_init(struct ddr_info *priv,
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const struct stm32mp1_ddr_config *config)
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{
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u32 pir;
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int ret;
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ret = board_ddr_power_init();
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if (ret)
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panic("ddr power init failed\n");
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debug("name = %s\n", config->info.name);
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debug("speed = %d MHz\n", config->info.speed);
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debug("size = 0x%x\n", config->info.size);
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/*
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* 1. Program the DWC_ddr_umctl2 registers
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* 1.1 RESETS: presetn, core_ddrc_rstn, aresetn
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*/
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/* Assert All DDR part */
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setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
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setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
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setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
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setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
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setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
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setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
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/* 1.2. start CLOCK */
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if (stm32mp1_ddr_clk_enable(priv, config->info.speed))
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panic("invalid DRAM clock : %d MHz\n",
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config->info.speed);
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/* 1.3. deassert reset */
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/* de-assert PHY rstn and ctl_rstn via DPHYRST and DPHYCTLRST */
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clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
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clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
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/* De-assert presetn once the clocks are active
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* and stable via DDRCAPBRST bit
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*/
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clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
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/* 1.4. wait 4 cycles for synchronization */
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asm(" nop");
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asm(" nop");
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asm(" nop");
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asm(" nop");
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/* 1.5. initialize registers ddr_umctl2 */
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/* Stop uMCTL2 before PHY is ready */
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clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
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debug("[0x%08x] dfimisc = 0x%08x\n",
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(u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
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set_reg(priv, REG_REG, &config->c_reg);
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set_reg(priv, REG_TIMING, &config->c_timing);
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set_reg(priv, REG_MAP, &config->c_map);
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/* skip CTRL init, SDRAM init is done by PHY PUBL */
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clrsetbits_le32(&priv->ctl->init0,
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DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK,
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DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL);
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set_reg(priv, REG_PERF, &config->c_perf);
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/* 2. deassert reset signal core_ddrc_rstn, aresetn and presetn */
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clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
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clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
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clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
|
|
|
|
/* 3. start PHY init by accessing relevant PUBL registers
|
|
* (DXGCR, DCR, PTR*, MR*, DTPR*)
|
|
*/
|
|
set_reg(priv, REGPHY_REG, &config->p_reg);
|
|
set_reg(priv, REGPHY_TIMING, &config->p_timing);
|
|
set_reg(priv, REGPHY_CAL, &config->p_cal);
|
|
|
|
/* 4. Monitor PHY init status by polling PUBL register PGSR.IDONE
|
|
* Perform DDR PHY DRAM initialization and Gate Training Evaluation
|
|
*/
|
|
ddrphy_idone_wait(priv->phy);
|
|
|
|
/* 5. Indicate to PUBL that controller performs SDRAM initialization
|
|
* by setting PIR.INIT and PIR CTLDINIT and pool PGSR.IDONE
|
|
* DRAM init is done by PHY, init0.skip_dram.init = 1
|
|
*/
|
|
pir = DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | DDRPHYC_PIR_ZCAL |
|
|
DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_DRAMINIT | DDRPHYC_PIR_ICPC;
|
|
|
|
if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
|
|
pir |= DDRPHYC_PIR_DRAMRST; /* only for DDR3 */
|
|
|
|
stm32mp1_ddrphy_init(priv->phy, pir);
|
|
|
|
/* 6. SET DFIMISC.dfi_init_complete_en to 1 */
|
|
/* Enable quasi-dynamic register programming*/
|
|
start_sw_done(priv->ctl);
|
|
setbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
|
|
wait_sw_done_ack(priv->ctl);
|
|
|
|
/* 7. Wait for DWC_ddr_umctl2 to move to normal operation mode
|
|
* by monitoring STAT.operating_mode signal
|
|
*/
|
|
/* wait uMCTL2 ready */
|
|
|
|
wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
|
|
|
|
debug("DDR DQS training : ");
|
|
/* 8. Disable Auto refresh and power down by setting
|
|
* - RFSHCTL3.dis_au_refresh = 1
|
|
* - PWRCTL.powerdown_en = 0
|
|
* - DFIMISC.dfiinit_complete_en = 0
|
|
*/
|
|
stm32mp1_refresh_disable(priv->ctl);
|
|
|
|
/* 9. Program PUBL PGCR to enable refresh during training and rank to train
|
|
* not done => keep the programed value in PGCR
|
|
*/
|
|
|
|
/* 10. configure PUBL PIR register to specify which training step to run */
|
|
/* warning : RVTRN is not supported by this PUBL */
|
|
stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN);
|
|
|
|
/* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
|
|
ddrphy_idone_wait(priv->phy);
|
|
|
|
/* 12. set back registers in step 8 to the orginal values if desidered */
|
|
stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
|
|
config->c_reg.pwrctl);
|
|
|
|
/* enable uMCTL2 AXI port 0 and 1 */
|
|
setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
|
|
setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
|
|
}
|