141 lines
3.1 KiB
C
141 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Altera SoCFPGA common board code
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*
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* Copyright (C) 2015 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/secure_vab.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <hang.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <usb.h>
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#include <usb/dwc2_udc.h>
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DECLARE_GLOBAL_DATA_PTR;
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void s_init(void) {
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#ifndef CONFIG_ARM64
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/*
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* Preconfigure ACTLR and CPACR, make sure Write Full Line of Zeroes
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* is disabled in ACTLR.
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* This is optional on CycloneV / ArriaV.
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* This is mandatory on Arria10, otherwise Linux refuses to boot.
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*/
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asm volatile(
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"mcr p15, 0, %0, c1, c0, 1\n"
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"mcr p15, 0, %0, c1, c0, 2\n"
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"isb\n"
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"dsb\n"
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::"r"(0x0));
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#endif
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}
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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/* Address of boot parameters for ATAG (if ATAG is used) */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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#ifdef CONFIG_USB_GADGET
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struct dwc2_plat_otg_data socfpga_otg_data = {
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.usb_gusbcfg = 0x1417,
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};
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int board_usb_init(int index, enum usb_init_type init)
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{
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int node[2], count;
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fdt_addr_t addr;
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count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
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COMPAT_ALTERA_SOCFPGA_DWC2USB,
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node, 2);
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if (count <= 0) /* No controller found. */
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return 0;
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addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
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if (addr == FDT_ADDR_T_NONE) {
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printf("UDC Controller has no 'reg' property!\n");
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return -EINVAL;
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}
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/* Patch the address from OF into the controller pdata. */
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socfpga_otg_data.regs_otg = addr;
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return dwc2_udc_probe(&socfpga_otg_data);
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}
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int g_dnl_board_usb_cable_connected(void)
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{
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return 1;
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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__weak int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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#if IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS)
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void board_fit_image_post_process(const void *fit, int node, void **p_image,
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size_t *p_size)
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{
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if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH)) {
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if (socfpga_vendor_authentication(p_image, p_size))
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hang();
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}
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}
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#endif
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#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
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void board_prep_linux(bootm_headers_t *images)
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{
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if (!images->fit_uname_cfg) {
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if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
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!IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
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/*
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* Ensure the OS is always booted from FIT and with
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* VAB signed certificate
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*/
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printf("Please use FIT with VAB signed images!\n");
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hang();
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}
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} else {
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/* Update fdt_addr in enviroment variable */
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env_set_hex("fdt_addr", (ulong)images->ft_addr);
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debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr);
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}
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if (IS_ENABLED(CONFIG_CADENCE_QSPI)) {
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if (env_get("linux_qspi_enable"))
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run_command(env_get("linux_qspi_enable"), 0);
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}
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}
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#endif
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