533 lines
15 KiB
C
533 lines
15 KiB
C
/*
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* Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2003 Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ppc_asm.tmpl>
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#include <linux/compiler.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
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#endif
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/* --------------------------------------------------------------- */
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void get_sys_info(sys_info_t *sys_info)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#ifdef CONFIG_FSL_IFC
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struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
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u32 ccr;
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#endif
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#ifdef CONFIG_FSL_CORENET
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volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
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unsigned int cpu;
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
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#endif
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const u8 core_cplx_PLL[16] = {
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[ 0] = 0, /* CC1 PPL / 1 */
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[ 1] = 0, /* CC1 PPL / 2 */
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[ 2] = 0, /* CC1 PPL / 4 */
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[ 4] = 1, /* CC2 PPL / 1 */
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[ 5] = 1, /* CC2 PPL / 2 */
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[ 6] = 1, /* CC2 PPL / 4 */
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[ 8] = 2, /* CC3 PPL / 1 */
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[ 9] = 2, /* CC3 PPL / 2 */
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[10] = 2, /* CC3 PPL / 4 */
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[12] = 3, /* CC4 PPL / 1 */
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[13] = 3, /* CC4 PPL / 2 */
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[14] = 3, /* CC4 PPL / 4 */
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};
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const u8 core_cplx_pll_div[16] = {
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[ 0] = 1, /* CC1 PPL / 1 */
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[ 1] = 2, /* CC1 PPL / 2 */
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[ 2] = 4, /* CC1 PPL / 4 */
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[ 4] = 1, /* CC2 PPL / 1 */
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[ 5] = 2, /* CC2 PPL / 2 */
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[ 6] = 4, /* CC2 PPL / 4 */
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[ 8] = 1, /* CC3 PPL / 1 */
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[ 9] = 2, /* CC3 PPL / 2 */
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[10] = 4, /* CC3 PPL / 4 */
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[12] = 1, /* CC4 PPL / 1 */
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[13] = 2, /* CC4 PPL / 2 */
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[14] = 4, /* CC4 PPL / 4 */
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};
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uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
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#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
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uint rcw_tmp;
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#endif
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uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
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unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
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uint mem_pll_rat;
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sys_info->freq_systembus = sysclk;
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#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
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uint ddr_refclk_sel;
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unsigned int porsr1_sys_clk;
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porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
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& FSL_DCFG_PORSR1_SYSCLK_MASK;
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if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
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sys_info->diff_sysclk = 1;
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else
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sys_info->diff_sysclk = 0;
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/*
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* DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
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* are driven by separate DDR Refclock or single source
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* differential clock.
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*/
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ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
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FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
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FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
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/*
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* For single source clocking, both ddrclock and sysclock
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* are driven by differential sysclock.
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*/
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if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
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sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
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else
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#endif
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#ifdef CONFIG_DDR_CLK_FREQ
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sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
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#else
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sys_info->freq_ddrbus = sysclk;
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#endif
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sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
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mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
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FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
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& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
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#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
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if (mem_pll_rat == 0) {
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mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
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FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
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FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
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}
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#endif
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/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
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* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
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* it uses 6.
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*/
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#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
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defined(CONFIG_PPC_T4080)
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if (SVR_MAJ(get_svr()) >= 2)
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mem_pll_rat *= 2;
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#endif
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if (mem_pll_rat > 2)
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sys_info->freq_ddrbus *= mem_pll_rat;
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else
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sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
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for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
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ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
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if (ratio[i] > 4)
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freq_c_pll[i] = sysclk * ratio[i];
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else
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freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
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}
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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/*
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* As per CHASSIS2 architeture total 12 clusters are posible and
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* Each cluster has up to 4 cores, sharing the same PLL selection.
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* The cluster clock assignment is SoC defined.
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*
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* Total 4 clock groups are possible with 3 PLLs each.
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* as per array indices, clock group A has 0, 1, 2 numbered PLLs &
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* clock group B has 3, 4, 6 and so on.
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*
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* Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
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* depends upon the SoC architeture. Same applies to other
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* clock groups and clusters.
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*
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*/
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for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
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int cluster = fsl_qoriq_core_to_cluster(cpu);
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u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
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& 0xf;
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u32 cplx_pll = core_cplx_PLL[c_pll_sel];
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cplx_pll += cc_group[cluster] - 1;
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sys_info->freq_processor[cpu] =
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freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
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}
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#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
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defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
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#define FM1_CLK_SEL 0xe0000000
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#define FM1_CLK_SHIFT 29
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#else
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#define PME_CLK_SEL 0xe0000000
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#define PME_CLK_SHIFT 29
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#define FM1_CLK_SEL 0x1c000000
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#define FM1_CLK_SHIFT 26
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#endif
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#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
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rcw_tmp = in_be32(&gur->rcwsr[7]);
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#endif
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#ifdef CONFIG_SYS_DPAA_PME
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#ifndef CONFIG_PME_PLAT_CLK_DIV
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switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
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case 1:
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sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
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break;
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case 2:
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sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
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break;
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case 3:
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sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
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break;
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case 4:
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sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
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break;
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case 6:
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sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
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break;
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case 7:
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sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
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break;
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default:
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printf("Error: Unknown PME clock select!\n");
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case 0:
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sys_info->freq_pme = sys_info->freq_systembus / 2;
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break;
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}
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#else
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sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
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#endif
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#endif
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#ifdef CONFIG_SYS_DPAA_QBMAN
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sys_info->freq_qman = sys_info->freq_systembus / 2;
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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#ifndef CONFIG_FM_PLAT_CLK_DIV
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switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
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case 1:
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sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
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break;
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case 2:
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sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
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break;
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case 3:
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sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
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break;
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case 4:
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sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
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break;
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case 5:
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sys_info->freq_fman[0] = sys_info->freq_systembus;
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break;
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case 6:
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sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
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break;
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case 7:
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sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
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break;
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default:
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printf("Error: Unknown FMan1 clock select!\n");
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case 0:
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sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
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break;
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}
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#if (CONFIG_SYS_NUM_FMAN) == 2
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#ifdef CONFIG_SYS_FM2_CLK
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#define FM2_CLK_SEL 0x00000038
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#define FM2_CLK_SHIFT 3
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rcw_tmp = in_be32(&gur->rcwsr[15]);
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switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
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case 1:
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sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
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break;
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case 2:
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sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
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break;
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case 3:
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sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
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break;
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case 4:
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sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
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break;
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case 5:
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sys_info->freq_fman[1] = sys_info->freq_systembus;
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break;
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case 6:
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sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
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break;
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case 7:
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sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
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break;
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default:
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printf("Error: Unknown FMan2 clock select!\n");
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case 0:
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sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
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break;
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}
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#endif
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#endif /* CONFIG_SYS_NUM_FMAN == 2 */
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#else
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sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
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#endif
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#endif
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#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
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for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
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u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
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& 0xf;
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u32 cplx_pll = core_cplx_PLL[c_pll_sel];
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sys_info->freq_processor[cpu] =
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freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
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}
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#define PME_CLK_SEL 0x80000000
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#define FM1_CLK_SEL 0x40000000
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#define FM2_CLK_SEL 0x20000000
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#define HWA_ASYNC_DIV 0x04000000
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#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
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#define HWA_CC_PLL 1
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#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
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#define HWA_CC_PLL 2
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#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
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#define HWA_CC_PLL 2
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#else
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#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
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#endif
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rcw_tmp = in_be32(&gur->rcwsr[7]);
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#ifdef CONFIG_SYS_DPAA_PME
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if (rcw_tmp & PME_CLK_SEL) {
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if (rcw_tmp & HWA_ASYNC_DIV)
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sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
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else
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sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
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} else {
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sys_info->freq_pme = sys_info->freq_systembus / 2;
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}
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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if (rcw_tmp & FM1_CLK_SEL) {
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if (rcw_tmp & HWA_ASYNC_DIV)
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sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
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else
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sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
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} else {
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sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
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}
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#if (CONFIG_SYS_NUM_FMAN) == 2
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if (rcw_tmp & FM2_CLK_SEL) {
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if (rcw_tmp & HWA_ASYNC_DIV)
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sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
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else
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sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
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} else {
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sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
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}
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#endif
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#endif
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#ifdef CONFIG_SYS_DPAA_QBMAN
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sys_info->freq_qman = sys_info->freq_systembus / 2;
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#endif
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#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
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#ifdef CONFIG_U_QE
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sys_info->freq_qe = sys_info->freq_systembus / 2;
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#endif
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#else /* CONFIG_FSL_CORENET */
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uint plat_ratio, e500_ratio, half_freq_systembus;
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int i;
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#ifdef CONFIG_QE
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__maybe_unused u32 qe_ratio;
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#endif
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plat_ratio = (gur->porpllsr) & 0x0000003e;
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plat_ratio >>= 1;
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sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
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/* Divide before multiply to avoid integer
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* overflow for processor speeds above 2GHz */
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half_freq_systembus = sys_info->freq_systembus/2;
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for (i = 0; i < cpu_numcores(); i++) {
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e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
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sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
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}
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/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
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sys_info->freq_ddrbus = sys_info->freq_systembus;
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#ifdef CONFIG_DDR_CLK_FREQ
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{
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u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
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>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
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if (ddr_ratio != 0x7)
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sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
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}
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#endif
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#ifdef CONFIG_QE
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#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
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sys_info->freq_qe = sys_info->freq_systembus;
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#else
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qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
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>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
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sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
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#endif
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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sys_info->freq_fman[0] = sys_info->freq_systembus;
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#endif
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#endif /* CONFIG_FSL_CORENET */
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#if defined(CONFIG_FSL_LBC)
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uint lcrr_div;
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#if defined(CONFIG_SYS_LBC_LCRR)
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/* We will program LCRR to this value later */
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lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
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#else
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lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
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#endif
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if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
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#if defined(CONFIG_FSL_CORENET)
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/* If this is corenet based SoC, bit-representation
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* for four times the clock divider values.
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*/
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lcrr_div *= 4;
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#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
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!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
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/*
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* Yes, the entire PQ38 family use the same
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* bit-representation for twice the clock divider values.
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*/
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lcrr_div *= 2;
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#endif
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sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
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} else {
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/* In case anyone cares what the unknown value is */
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sys_info->freq_localbus = lcrr_div;
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|
}
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|
#endif
|
|
|
|
#if defined(CONFIG_FSL_IFC)
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|
ccr = ifc_in32(&ifc_regs->ifc_ccr);
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ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
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|
|
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sys_info->freq_localbus = sys_info->freq_systembus / ccr;
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|
#endif
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|
}
|
|
|
|
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int get_clocks (void)
|
|
{
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|
sys_info_t sys_info;
|
|
#ifdef CONFIG_MPC8544
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|
volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
|
#endif
|
|
#if defined(CONFIG_CPM2)
|
|
volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
|
|
uint sccr, dfbrg;
|
|
|
|
/* set VCO = 4 * BRG */
|
|
cpm->im_cpm_intctl.sccr &= 0xfffffffc;
|
|
sccr = cpm->im_cpm_intctl.sccr;
|
|
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
|
|
#endif
|
|
get_sys_info (&sys_info);
|
|
gd->cpu_clk = sys_info.freq_processor[0];
|
|
gd->bus_clk = sys_info.freq_systembus;
|
|
gd->mem_clk = sys_info.freq_ddrbus;
|
|
gd->arch.lbc_clk = sys_info.freq_localbus;
|
|
|
|
#ifdef CONFIG_QE
|
|
gd->arch.qe_clk = sys_info.freq_qe;
|
|
gd->arch.brg_clk = gd->arch.qe_clk / 2;
|
|
#endif
|
|
/*
|
|
* The base clock for I2C depends on the actual SOC. Unfortunately,
|
|
* there is no pattern that can be used to determine the frequency, so
|
|
* the only choice is to look up the actual SOC number and use the value
|
|
* for that SOC. This information is taken from application note
|
|
* AN2919.
|
|
*/
|
|
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
|
|
defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
|
|
defined(CONFIG_P1022)
|
|
gd->arch.i2c1_clk = sys_info.freq_systembus;
|
|
#elif defined(CONFIG_MPC8544)
|
|
/*
|
|
* On the 8544, the I2C clock is the same as the SEC clock. This can be
|
|
* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
|
|
* 4.4.3.3 of the 8544 RM. Note that this might actually work for all
|
|
* 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
|
|
* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
|
|
*/
|
|
if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
|
|
gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
|
|
else
|
|
gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
|
|
#else
|
|
/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
|
|
gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
|
|
#endif
|
|
gd->arch.i2c2_clk = gd->arch.i2c1_clk;
|
|
|
|
#if defined(CONFIG_FSL_ESDHC)
|
|
#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
|
|
defined(CONFIG_P1014)
|
|
gd->arch.sdhc_clk = gd->bus_clk;
|
|
#else
|
|
gd->arch.sdhc_clk = gd->bus_clk / 2;
|
|
#endif
|
|
#endif /* defined(CONFIG_FSL_ESDHC) */
|
|
|
|
#if defined(CONFIG_CPM2)
|
|
gd->arch.vco_out = 2*sys_info.freq_systembus;
|
|
gd->arch.cpm_clk = gd->arch.vco_out / 2;
|
|
gd->arch.scc_clk = gd->arch.vco_out / 4;
|
|
gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
|
|
#endif
|
|
|
|
if(gd->cpu_clk != 0) return (0);
|
|
else return (1);
|
|
}
|
|
|
|
|
|
/********************************************
|
|
* get_bus_freq
|
|
* return system bus freq in Hz
|
|
*********************************************/
|
|
ulong get_bus_freq (ulong dummy)
|
|
{
|
|
return gd->bus_clk;
|
|
}
|
|
|
|
/********************************************
|
|
* get_ddr_freq
|
|
* return ddr bus freq in Hz
|
|
*********************************************/
|
|
ulong get_ddr_freq (ulong dummy)
|
|
{
|
|
return gd->mem_clk;
|
|
}
|