75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
/*
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* (C) Copyright 2007
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#if defined(CONFIG_CMD_NAND)
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#include <nand.h>
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#include <asm/processor.h>
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#define readb(addr) *(volatile u_char *)(addr)
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#define readl(addr) *(volatile u_long *)(addr)
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#define writeb(d,addr) *(volatile u_char *)(addr) = (d)
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#define SC3_NAND_ALE 29 /* GPIO PIN 3 */
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#define SC3_NAND_CLE 30 /* GPIO PIN 2 */
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#define SC3_NAND_CE 27 /* GPIO PIN 5 */
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static void *sc3_io_base;
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static void *sc3_control_base = (void *)0xEF600700;
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static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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if ( ctrl & NAND_CLE )
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set_bit (SC3_NAND_CLE, sc3_control_base);
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else
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clear_bit (SC3_NAND_CLE, sc3_control_base);
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if ( ctrl & NAND_ALE )
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set_bit (SC3_NAND_ALE, sc3_control_base);
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else
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clear_bit (SC3_NAND_ALE, sc3_control_base);
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if ( ctrl & NAND_NCE )
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set_bit (SC3_NAND_CE, sc3_control_base);
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else
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clear_bit (SC3_NAND_CE, sc3_control_base);
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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static int sc3_nand_dev_ready(struct mtd_info *mtd)
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{
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if (!(readl(sc3_control_base + 0x1C) & 0x4000))
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return 0;
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return 1;
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}
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static void sc3_select_chip(struct mtd_info *mtd, int chip)
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{
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clear_bit (SC3_NAND_CE, sc3_control_base);
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}
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int board_nand_init(struct nand_chip *nand)
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{
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nand->ecc.mode = NAND_ECC_SOFT;
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sc3_io_base = (void *) CONFIG_SYS_NAND_BASE;
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/* Set address of NAND IO lines (Using Linear Data Access Region) */
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nand->IO_ADDR_R = (void __iomem *) sc3_io_base;
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nand->IO_ADDR_W = (void __iomem *) sc3_io_base;
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/* Reference hardware control function */
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nand->cmd_ctrl = sc3_nand_hwcontrol;
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nand->dev_ready = sc3_nand_dev_ready;
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nand->select_chip = sc3_select_chip;
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return 0;
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}
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#endif
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