41 lines
667 B
C
41 lines
667 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _DDR3_TRAINING_IP_PBS_H_
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#define _DDR3_TRAINING_IP_PBS_H_
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enum {
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EBA_CONFIG,
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EEBA_CONFIG,
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SBA_CONFIG
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};
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enum hws_training_load_op {
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TRAINING_LOAD_OPERATION_UNLOAD,
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TRAINING_LOAD_OPERATION_LOAD
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};
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enum hws_edge {
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TRAINING_EDGE_1,
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TRAINING_EDGE_2
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};
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enum hws_edge_search {
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TRAINING_EDGE_MAX,
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TRAINING_EDGE_MIN
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};
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enum pbs_dir {
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PBS_TX_MODE = 0,
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PBS_RX_MODE,
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NUM_OF_PBS_MODES
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};
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int ddr3_tip_pbs_rx(u32 dev_num);
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int ddr3_tip_print_all_pbs_result(u32 dev_num);
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int ddr3_tip_pbs_tx(u32 dev_num);
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#endif /* _DDR3_TRAINING_IP_PBS_H_ */
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