54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/cache.h>
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#include <watchdog.h>
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void flush_cache (ulong start_addr, ulong size)
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{
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#ifndef CONFIG_5xx
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ulong addr, end_addr = start_addr + size;
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if (CFG_CACHELINE_SIZE) {
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addr = start_addr & (CFG_CACHELINE_SIZE - 1);
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for (addr = start_addr;
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addr < end_addr;
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addr += CFG_CACHELINE_SIZE) {
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asm ("dcbst 0,%0": :"r" (addr));
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WATCHDOG_RESET();
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}
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asm ("sync"); /* Wait for all dcbst to complete on bus */
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for (addr = start_addr;
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addr < end_addr;
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addr += CFG_CACHELINE_SIZE) {
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asm ("icbi 0,%0": :"r" (addr));
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WATCHDOG_RESET();
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}
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}
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asm ("sync"); /* Always flush prefetch queue in any case */
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asm ("isync");
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#endif
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}
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