393 lines
9.9 KiB
C
393 lines
9.9 KiB
C
/*
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* (C) Copyright 2007-2009 Michal Simek
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* (C) Copyright 2003 Xilinx Inc.
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <net.h>
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#include <config.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <fdtdec.h>
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#undef DEBUG
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#define ENET_ADDR_LENGTH 6
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/* EmacLite constants */
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#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
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#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
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#define XEL_TSR_OFFSET 0x07FC /* Tx status */
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#define XEL_RSR_OFFSET 0x17FC /* Rx status */
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#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
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/* Xmit complete */
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#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
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/* Xmit interrupt enable bit */
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#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
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/* Buffer is active, SW bit only */
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#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
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/* Program the MAC address */
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#define XEL_TSR_PROGRAM_MASK 0x00000002UL
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/* define for programming the MAC address into the EMAC Lite */
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#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
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/* Transmit packet length upper byte */
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#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
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/* Transmit packet length lower byte */
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#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
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/* Recv complete */
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#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
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/* Recv interrupt enable bit */
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#define XEL_RSR_RECV_IE_MASK 0x00000008UL
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struct xemaclite {
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u32 nexttxbuffertouse; /* Next TX buffer to write to */
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u32 nextrxbuffertouse; /* Next RX buffer to read from */
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u32 txpp; /* TX ping pong buffer */
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u32 rxpp; /* RX ping pong buffer */
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};
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static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
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static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
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{
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u32 i;
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u32 alignbuffer;
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u32 *to32ptr;
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u32 *from32ptr;
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u8 *to8ptr;
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u8 *from8ptr;
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from32ptr = (u32 *) srcptr;
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/* Word aligned buffer, no correction needed. */
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to32ptr = (u32 *) destptr;
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while (bytecount > 3) {
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*to32ptr++ = *from32ptr++;
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bytecount -= 4;
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}
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to8ptr = (u8 *) to32ptr;
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alignbuffer = *from32ptr++;
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from8ptr = (u8 *) &alignbuffer;
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for (i = 0; i < bytecount; i++)
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*to8ptr++ = *from8ptr++;
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}
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static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
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{
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u32 i;
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u32 alignbuffer;
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u32 *to32ptr = (u32 *) destptr;
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u32 *from32ptr;
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u8 *to8ptr;
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u8 *from8ptr;
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from32ptr = (u32 *) srcptr;
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while (bytecount > 3) {
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*to32ptr++ = *from32ptr++;
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bytecount -= 4;
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}
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alignbuffer = 0;
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to8ptr = (u8 *) &alignbuffer;
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from8ptr = (u8 *) from32ptr;
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for (i = 0; i < bytecount; i++)
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*to8ptr++ = *from8ptr++;
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*to32ptr++ = alignbuffer;
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}
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static void emaclite_halt(struct eth_device *dev)
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{
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debug("eth_halt\n");
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}
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static int emaclite_init(struct eth_device *dev, bd_t *bis)
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{
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struct xemaclite *emaclite = dev->priv;
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debug("EmacLite Initialization Started\n");
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/*
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* TX - TX_PING & TX_PONG initialization
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*/
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/* Restart PING TX */
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out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
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/* Copy MAC address */
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xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
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/* Set the length */
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out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
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/* Update the MAC address in the EMAC Lite */
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out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
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/* Wait for EMAC Lite to finish with the MAC address update */
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while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
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XEL_TSR_PROG_MAC_ADDR) != 0)
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;
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if (emaclite->txpp) {
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/* The same operation with PONG TX */
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out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
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xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
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XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
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out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
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out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
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XEL_TSR_PROG_MAC_ADDR);
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while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
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XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
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;
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}
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/*
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* RX - RX_PING & RX_PONG initialization
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*/
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/* Write out the value to flush the RX buffer */
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out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
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if (emaclite->rxpp)
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out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
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XEL_RSR_RECV_IE_MASK);
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debug("EmacLite Initialization complete\n");
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return 0;
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}
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static int xemaclite_txbufferavailable(struct eth_device *dev)
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{
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u32 reg;
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u32 txpingbusy;
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u32 txpongbusy;
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struct xemaclite *emaclite = dev->priv;
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/*
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* Read the other buffer register
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* and determine if the other buffer is available
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*/
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reg = in_be32 (dev->iobase +
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emaclite->nexttxbuffertouse + 0);
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txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
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XEL_TSR_XMIT_BUSY_MASK);
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reg = in_be32 (dev->iobase +
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(emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
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txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
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XEL_TSR_XMIT_BUSY_MASK);
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return !(txpingbusy && txpongbusy);
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}
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static int emaclite_send(struct eth_device *dev, void *ptr, int len)
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{
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u32 reg;
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u32 baseaddress;
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struct xemaclite *emaclite = dev->priv;
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u32 maxtry = 1000;
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if (len > PKTSIZE)
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len = PKTSIZE;
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while (!xemaclite_txbufferavailable(dev) && maxtry) {
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udelay(10);
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maxtry--;
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}
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if (!maxtry) {
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printf("Error: Timeout waiting for ethernet TX buffer\n");
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/* Restart PING TX */
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out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
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if (emaclite->txpp) {
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out_be32 (dev->iobase + XEL_TSR_OFFSET +
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XEL_BUFFER_OFFSET, 0);
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}
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return -1;
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}
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/* Determine the expected TX buffer address */
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baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
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/* Determine if the expected buffer address is empty */
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reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
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if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
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&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
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& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
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if (emaclite->txpp)
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emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
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debug("Send packet from 0x%x\n", baseaddress);
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/* Write the frame to the buffer */
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xemaclite_alignedwrite(ptr, baseaddress, len);
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out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
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(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
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reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
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reg |= XEL_TSR_XMIT_BUSY_MASK;
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if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
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reg |= XEL_TSR_XMIT_ACTIVE_MASK;
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out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
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return 0;
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}
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if (emaclite->txpp) {
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/* Switch to second buffer */
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baseaddress ^= XEL_BUFFER_OFFSET;
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/* Determine if the expected buffer address is empty */
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reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
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if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
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&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
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& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
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debug("Send packet from 0x%x\n", baseaddress);
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/* Write the frame to the buffer */
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xemaclite_alignedwrite(ptr, baseaddress, len);
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out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
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(XEL_TPLR_LENGTH_MASK_HI |
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XEL_TPLR_LENGTH_MASK_LO)));
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reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
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reg |= XEL_TSR_XMIT_BUSY_MASK;
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if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
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reg |= XEL_TSR_XMIT_ACTIVE_MASK;
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out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
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return 0;
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}
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}
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puts("Error while sending frame\n");
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return -1;
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}
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static int emaclite_recv(struct eth_device *dev)
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{
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u32 length;
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u32 reg;
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u32 baseaddress;
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struct xemaclite *emaclite = dev->priv;
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baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
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reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
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debug("Testing data at address 0x%x\n", baseaddress);
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if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
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if (emaclite->rxpp)
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emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
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} else {
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if (!emaclite->rxpp) {
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debug("No data was available - address 0x%x\n",
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baseaddress);
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return 0;
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} else {
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baseaddress ^= XEL_BUFFER_OFFSET;
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reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
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if ((reg & XEL_RSR_RECV_DONE_MASK) !=
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XEL_RSR_RECV_DONE_MASK) {
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debug("No data was available - address 0x%x\n",
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baseaddress);
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return 0;
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}
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}
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}
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/* Get the length of the frame that arrived */
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switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
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0xFFFF0000 ) >> 16) {
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case 0x806:
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length = 42 + 20; /* FIXME size of ARP */
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debug("ARP Packet\n");
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break;
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case 0x800:
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length = 14 + 14 +
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(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
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0x10))) & 0xFFFF0000) >> 16);
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/* FIXME size of IP packet */
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debug ("IP Packet\n");
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break;
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default:
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debug("Other Packet\n");
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length = PKTSIZE;
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break;
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}
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xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
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etherrxbuff, length);
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/* Acknowledge the frame */
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reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
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reg &= ~XEL_RSR_RECV_DONE_MASK;
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out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
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debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
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net_process_received_packet((uchar *)etherrxbuff, length);
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return length;
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}
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int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
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int txpp, int rxpp)
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{
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struct eth_device *dev;
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struct xemaclite *emaclite;
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dev = calloc(1, sizeof(*dev));
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if (dev == NULL)
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return -1;
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emaclite = calloc(1, sizeof(struct xemaclite));
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if (emaclite == NULL) {
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free(dev);
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return -1;
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}
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dev->priv = emaclite;
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emaclite->txpp = txpp;
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emaclite->rxpp = rxpp;
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sprintf(dev->name, "Xelite.%lx", base_addr);
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dev->iobase = base_addr;
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dev->init = emaclite_init;
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dev->halt = emaclite_halt;
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dev->send = emaclite_send;
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dev->recv = emaclite_recv;
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eth_register(dev);
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return 1;
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}
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#ifdef CONFIG_OF_CONTROL
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int xilinx_emaclite_of_init(const void *blob)
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{
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int offset = 0;
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u32 ret = 0;
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u32 reg;
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do {
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offset = fdt_node_offset_by_compatible(blob, offset,
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"xlnx,xps-ethernetlite-1.00.a");
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if (offset != -1) {
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reg = fdtdec_get_addr(blob, offset, "reg");
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if (reg != FDT_ADDR_T_NONE) {
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u32 rxpp = fdtdec_get_int(blob, offset,
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"xlnx,rx-ping-pong", 0);
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u32 txpp = fdtdec_get_int(blob, offset,
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"xlnx,tx-ping-pong", 0);
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ret |= xilinx_emaclite_initialize(NULL, reg,
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txpp, rxpp);
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} else {
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debug("EMACLITE: Can't get base address\n");
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return -1;
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}
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}
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} while (offset != -1);
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return ret;
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}
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#endif
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