363 lines
7.6 KiB
C
363 lines
7.6 KiB
C
/*
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* (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
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*
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* Developed for DENX Software Engineering GmbH
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/* This test performs testing of FPGA SCRATCH register,
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* gets FPGA version and run get_ram_size() on FPGA memory
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*/
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#include <post.h>
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#include <watchdog.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define FPGA_SCRATCH_REG 0xC4000050
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#define FPGA_VERSION_REG 0xC4000040
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#define FPGA_RAM_START 0xC4200000
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#define FPGA_RAM_END 0xC4203FFF
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#define FPGA_STAT 0xC400000C
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#define FPGA_BUFFER 0x00800000
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#define FPGA_RAM_SIZE (FPGA_RAM_END - FPGA_RAM_START + 1)
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#if CONFIG_POST & CONFIG_SYS_POST_BSPEC3
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const static unsigned long pattern[] = {
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0xffffffff,
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0xaaaaaaaa,
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0xcccccccc,
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0xf0f0f0f0,
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0xff00ff00,
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0xffff0000,
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0x0000ffff,
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0x00ff00ff,
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0x0f0f0f0f,
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0x33333333,
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0x55555555,
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0x00000000,
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};
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const static unsigned long otherpattern = 0x01234567;
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static int one_scratch_test(uint value)
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{
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uint read_value;
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int ret = 0;
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out_be32((void *)FPGA_SCRATCH_REG, value);
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/* read other location (protect against data lines capacity) */
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ret = in_be16((void *)FPGA_VERSION_REG);
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/* verify test pattern */
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read_value = in_be32((void *)FPGA_SCRATCH_REG);
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if (read_value != value) {
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post_log("FPGA SCRATCH test failed write %08X, read %08X\n",
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value, read_value);
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ret = -1;
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}
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return ret;
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}
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static int fpga_post_test1(ulong *start, ulong size, ulong val)
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{
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int ret = 0;
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ulong i = 0;
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ulong *mem = start;
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ulong readback;
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for (i = 0; i < size / sizeof(ulong); i++) {
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mem[i] = val;
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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for (i = 0; i < size / sizeof(ulong); i++) {
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readback = mem[i];
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if (readback != val) {
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post_log("FPGA Memory error at %08x, "
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"wrote %08x, read %08x !\n",
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mem + i, val, readback);
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ret = -1;
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break;
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}
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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return ret;
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}
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static int fpga_post_test2(ulong *start, ulong size)
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{
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int ret = 0;
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ulong i = 0;
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ulong *mem = start;
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ulong readback;
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for (i = 0; i < size / sizeof(ulong); i++) {
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mem[i] = 1 << (i % 32);
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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for (i = 0; i < size / sizeof(ulong); i++) {
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readback = mem[i];
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if (readback != 1 << (i % 32)) {
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post_log("FPGA Memory error at %08x, "
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"wrote %08x, read %08x !\n",
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mem + i, 1 << (i % 32), readback);
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ret = -1;
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break;
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}
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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return ret;
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}
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static int fpga_post_test3(ulong *start, ulong size)
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{
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int ret = 0;
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ulong i = 0;
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ulong *mem = start;
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ulong readback;
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for (i = 0; i < size / sizeof(ulong); i++) {
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mem[i] = i;
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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for (i = 0; i < size / sizeof(ulong); i++) {
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readback = mem[i];
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if (readback != i) {
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post_log("FPGA Memory error at %08x, "
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"wrote %08x, read %08x !\n",
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mem + i, i, readback);
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ret = -1;
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break;
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}
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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return ret;
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}
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static int fpga_post_test4(ulong *start, ulong size)
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{
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int ret = 0;
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ulong i = 0;
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ulong *mem = start;
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ulong readback;
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for (i = 0; i < size / sizeof(ulong); i++) {
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mem[i] = ~i;
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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for (i = 0; i < size / sizeof(ulong); i++) {
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readback = mem[i];
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if (readback != ~i) {
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post_log("FPGA Memory error at %08x, "
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"wrote %08x, read %08x !\n",
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mem + i, ~i, readback);
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ret = -1;
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break;
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}
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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return ret;
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}
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/* FPGA Memory-pattern-test */
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static int fpga_mem_test(void)
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{
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int ret = 0;
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ulong* start = (ulong *)FPGA_RAM_START;
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ulong size = FPGA_RAM_SIZE;
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if (ret == 0)
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ret = fpga_post_test1(start, size, 0x00000000);
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if (ret == 0)
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ret = fpga_post_test1(start, size, 0xffffffff);
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if (ret == 0)
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ret = fpga_post_test1(start, size, 0x55555555);
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if (ret == 0)
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ret = fpga_post_test1(start, size, 0xaaaaaaaa);
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WATCHDOG_RESET();
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if (ret == 0)
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ret = fpga_post_test2(start, size);
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if (ret == 0)
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ret = fpga_post_test3(start, size);
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if (ret == 0)
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ret = fpga_post_test4(start, size);
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return ret;
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}
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/* Verify FPGA addresslines */
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static int fpga_post_addrline(ulong *address, ulong *base, ulong size)
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{
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unsigned long *target;
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unsigned long *end;
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unsigned long readback;
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unsigned long xor;
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int ret = 0;
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end = (ulong *)((ulong)base + size);
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xor = 0;
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for (xor = sizeof(ulong); xor > 0; xor <<= 1) {
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target = (ulong*)((ulong)address ^ xor);
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if ((target >= base) && (target < end)) {
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*address = ~*target;
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readback = *target;
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if (readback == *address) {
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post_log("Memory (address line) error at %08x"
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"XOR value %08x !\n",
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address, target, xor);
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ret = -1;
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break;
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}
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}
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}
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return ret;
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}
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/* Verify FPGA addresslines */
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static int fpga_post_dataline(ulong *address)
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{
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unsigned long temp32 = 0;
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int i = 0;
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int ret = 0;
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for (i = 0; i < ARRAY_SIZE(pattern); i++) {
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*address = pattern[i];
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/*
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* Put a different pattern on the data lines: otherwise they
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* may float long enough to read back what we wrote.
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*/
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*(address + 1) = otherpattern;
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temp32 = *address;
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if (temp32 != pattern[i]){
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post_log("Memory (date line) error at %08x, "
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"wrote %08x, read %08x !\n",
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address, pattern[i], temp32);
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ret = 1;
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}
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}
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return ret;
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}
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/* Verify FPGA, get version & memory size */
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int fpga_post_test(int flags)
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{
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uint old_value;
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uint version;
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uint read_value;
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int ret = 0;
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post_log("\n");
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old_value = in_be32((void *)FPGA_SCRATCH_REG);
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if (one_scratch_test(0x55555555))
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ret = 1;
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if (one_scratch_test(0xAAAAAAAA))
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ret = 1;
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out_be32((void *)FPGA_SCRATCH_REG, old_value);
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version = in_be32((void *)FPGA_VERSION_REG);
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post_log("FPGA version %u.%u\n",
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(version >> 8) & 0xFF, version & 0xFF);
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/* Enable write to FPGA RAM */
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out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
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/* get RAM size */
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read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, FPGA_RAM_SIZE);
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post_log("FPGA RAM size %d bytes\n", read_value);
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WATCHDOG_RESET();
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/* copy fpga memory to DDR2 RAM*/
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memcpy((void *)FPGA_BUFFER,(void *)FPGA_RAM_START, FPGA_RAM_SIZE);
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WATCHDOG_RESET();
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/* Test datalines */
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if (fpga_post_dataline((ulong *)FPGA_RAM_START)) {
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ret = 1;
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goto out;
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}
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WATCHDOG_RESET();
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/* Test addresslines */
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if (fpga_post_addrline((ulong *)FPGA_RAM_START,
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(ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) {
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ret = 1;
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goto out;
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}
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WATCHDOG_RESET();
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if (fpga_post_addrline((ulong *)FPGA_RAM_END - sizeof(long),
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(ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) {
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ret = 1;
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goto out;
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}
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WATCHDOG_RESET();
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/* Memory Pattern Test */
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if (fpga_mem_test()) {
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ret = 1;
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goto out;
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}
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WATCHDOG_RESET();
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/* restore memory */
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memcpy((void *)FPGA_RAM_START,(void *)FPGA_BUFFER, FPGA_RAM_SIZE);
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WATCHDOG_RESET();
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out:
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/* Disable write to RAM */
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out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) & 0xEFFF);
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return ret;
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}
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#endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC3 */
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