45 lines
1.9 KiB
Plaintext
45 lines
1.9 KiB
Plaintext
How to enable PMECC(Programmable Multibit ECC) for nand on Atmel SoCs
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2012-08-22 Josh Wu <josh.wu@atmel.com>
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The Programmable Multibit ECC (PMECC) controller is a programmable binary
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BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller
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can be used to support both SLC and MLC NAND Flash devices. It supports to
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generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector (512 or
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1024 bytes) of data.
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Following Atmel AT91 products support PMECC.
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- AT91SAM9X25, X35, G25, G15, G35 (tested)
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- AT91SAM9N12 (not tested, Should work)
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As soon as your nand flash software ECC works, you can enable PMECC.
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To use PMECC in this driver, the user needs to set:
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1. the PMECC correction error bits capability: CONFIG_PMECC_CAP.
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It can be 2, 4, 8, 12 or 24.
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2. The PMECC sector size: CONFIG_PMECC_SECTOR_SIZE.
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It only can be 512 or 1024.
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3. The PMECC index lookup table's offsets in ROM code: CONFIG_PMECC_INDEX_TABLE_OFFSET.
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In the chip datasheet section "Boot Stragegies", you can find
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two Galois Field Table in the ROM code. One table is for 512-bytes
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sector. Another is for 1024-byte sector. Each Galois Field includes
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two sub-table: indext table & alpha table.
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In the beginning of each Galois Field Table is the index table,
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Alpha table is in the following.
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So the index table's offset is same as the Galois Field Table.
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Please set CONFIG_PMECC_INDEX_TABLE_OFFSET correctly according the
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Galois Field Table's offset base on the sector size you used.
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Take AT91SAM9X5EK as an example, the board definition file likes:
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/* PMECC & PMERRLOC */
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#define CONFIG_ATMEL_NAND_HWECC 1
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#define CONFIG_ATMEL_NAND_HW_PMECC 1
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#define CONFIG_PMECC_CAP 2
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#define CONFIG_PMECC_SECTOR_SIZE 512
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#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000
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NOTE: If you use 1024 as the sector size, then need set 0x10000 as the
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CONFIG_PMECC_INDEX_TABLE_OFFSET
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