382 lines
8.7 KiB
C
382 lines
8.7 KiB
C
/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Manikandan Pillai <mani.pillai@ti.com>
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*
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* Derived from Beagle Board and 3430 SDP code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h> /* get mem tables */
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#include <asm/arch/sys_proto.h>
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#include <asm/bootm.h>
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#include <i2c.h>
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#include <linux/compiler.h>
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extern omap3_sysinfo sysinfo;
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static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
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#ifdef CONFIG_DISPLAY_CPUINFO
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static char *rev_s[CPU_3XX_MAX_REV] = {
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"1.0",
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"2.0",
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"2.1",
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"3.0",
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"3.1",
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"UNKNOWN",
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"UNKNOWN",
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"3.1.2"};
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/* this is the revision table for 37xx CPUs */
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static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
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"1.0",
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"1.1",
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"1.2"};
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#endif /* CONFIG_DISPLAY_CPUINFO */
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void omap_die_id(unsigned int *die_id)
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{
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struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
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die_id[0] = readl(&id_base->die_id_0);
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die_id[1] = readl(&id_base->die_id_1);
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die_id[2] = readl(&id_base->die_id_2);
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die_id[3] = readl(&id_base->die_id_3);
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}
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/******************************************
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* get_cpu_type(void) - extract cpu info
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******************************************/
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u32 get_cpu_type(void)
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{
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return readl(&ctrl_base->ctrl_omap_stat);
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}
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/******************************************
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* get_cpu_id(void) - extract cpu id
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* returns 0 for ES1.0, cpuid otherwise
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******************************************/
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u32 get_cpu_id(void)
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{
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struct ctrl_id *id_base;
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u32 cpuid = 0;
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/*
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* On ES1.0 the IDCODE register is not exposed on L4
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* so using CPU ID to differentiate between ES1.0 and > ES1.0.
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*/
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__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
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if ((cpuid & 0xf) == 0x0) {
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return 0;
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} else {
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/* Decode the IDs on > ES1.0 */
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id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
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cpuid = readl(&id_base->idcode);
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}
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return cpuid;
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}
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/******************************************
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* get_cpu_family(void) - extract cpu info
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******************************************/
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u32 get_cpu_family(void)
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{
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u16 hawkeye;
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u32 cpu_family;
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u32 cpuid = get_cpu_id();
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if (cpuid == 0)
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return CPU_OMAP34XX;
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hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
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switch (hawkeye) {
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case HAWKEYE_OMAP34XX:
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cpu_family = CPU_OMAP34XX;
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break;
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case HAWKEYE_AM35XX:
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cpu_family = CPU_AM35XX;
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break;
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case HAWKEYE_OMAP36XX:
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cpu_family = CPU_OMAP36XX;
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break;
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default:
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cpu_family = CPU_OMAP34XX;
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}
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return cpu_family;
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}
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/******************************************
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* get_cpu_rev(void) - extract version info
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******************************************/
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u32 get_cpu_rev(void)
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{
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u32 cpuid = get_cpu_id();
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if (cpuid == 0)
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return CPU_3XX_ES10;
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else
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return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
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}
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/*****************************************************************
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* get_sku_id(void) - read sku_id to get info on max clock rate
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*****************************************************************/
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u32 get_sku_id(void)
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{
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struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
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return readl(&id_base->sku_id) & SKUID_CLK_MASK;
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}
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/***************************************************************************
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* get_gpmc0_base() - Return current address hardware will be
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* fetching from. The below effectively gives what is correct, its a bit
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* mis-leading compared to the TRM. For the most general case the mask
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* needs to be also taken into account this does work in practice.
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* - for u-boot we currently map:
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* -- 0 to nothing,
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* -- 4 to flash
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* -- 8 to enent
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* -- c to wifi
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****************************************************************************/
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u32 get_gpmc0_base(void)
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{
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u32 b;
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b = readl(&gpmc_cfg->cs[0].config7);
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b &= 0x1F; /* keep base [5:0] */
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b = b << 24; /* ret 0x0b000000 */
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return b;
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}
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/*******************************************************************
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* get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
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*******************************************************************/
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u32 get_gpmc0_width(void)
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{
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return WIDTH_16BIT;
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}
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/*************************************************************************
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* get_board_rev() - setup to pass kernel board revision information
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* returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
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*************************************************************************/
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#ifdef CONFIG_REVISION_TAG
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u32 __weak get_board_rev(void)
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{
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return 0x20;
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}
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#endif
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/********************************************************
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* get_base(); get upper addr of current execution
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*******************************************************/
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static u32 get_base(void)
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{
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u32 val;
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__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
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val &= 0xF0000000;
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val >>= 28;
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return val;
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}
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/********************************************************
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* is_running_in_flash() - tell if currently running in
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* FLASH.
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*******************************************************/
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u32 is_running_in_flash(void)
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{
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if (get_base() < 4)
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return 1; /* in FLASH */
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return 0; /* running in SRAM or SDRAM */
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}
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/********************************************************
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* is_running_in_sram() - tell if currently running in
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* SRAM.
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*******************************************************/
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u32 is_running_in_sram(void)
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{
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if (get_base() == 4)
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return 1; /* in SRAM */
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return 0; /* running in FLASH or SDRAM */
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}
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/********************************************************
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* is_running_in_sdram() - tell if currently running in
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* SDRAM.
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*******************************************************/
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u32 is_running_in_sdram(void)
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{
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if (get_base() > 4)
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return 1; /* in SDRAM */
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return 0; /* running in SRAM or FLASH */
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}
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/***************************************************************
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* get_boot_type() - Is this an XIP type device or a stream one
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* bits 4-0 specify type. Bit 5 says mem/perif
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***************************************************************/
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u32 get_boot_type(void)
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{
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return (readl(&ctrl_base->status) & SYSBOOT_MASK);
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}
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/*************************************************************
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* get_device_type(): tell if GP/HS/EMU/TST
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*************************************************************/
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u32 get_device_type(void)
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{
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return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
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}
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#ifdef CONFIG_DISPLAY_CPUINFO
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/**
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* Print CPU information
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*/
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int print_cpuinfo (void)
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{
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char *cpu_family_s, *cpu_s, *sec_s, *max_clk;
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switch (get_cpu_family()) {
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case CPU_OMAP34XX:
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cpu_family_s = "OMAP";
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switch (get_cpu_type()) {
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case OMAP3503:
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cpu_s = "3503";
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break;
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case OMAP3515:
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cpu_s = "3515";
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break;
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case OMAP3525:
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cpu_s = "3525";
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break;
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case OMAP3530:
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cpu_s = "3530";
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break;
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default:
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cpu_s = "35XX";
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break;
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}
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if ((get_cpu_rev() >= CPU_3XX_ES31) &&
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(get_sku_id() == SKUID_CLK_720MHZ))
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max_clk = "720 MHz";
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else
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max_clk = "600 MHz";
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break;
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case CPU_AM35XX:
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cpu_family_s = "AM";
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switch (get_cpu_type()) {
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case AM3505:
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cpu_s = "3505";
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break;
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case AM3517:
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cpu_s = "3517";
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break;
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default:
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cpu_s = "35XX";
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break;
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}
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max_clk = "600 MHz";
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break;
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case CPU_OMAP36XX:
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switch (get_cpu_type()) {
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case AM3703:
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cpu_family_s = "AM";
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cpu_s = "3703";
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max_clk = "800 MHz";
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break;
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case AM3703_1GHZ:
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cpu_family_s = "AM";
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cpu_s = "3703";
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max_clk = "1 GHz";
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break;
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case AM3715:
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cpu_family_s = "AM";
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cpu_s = "3715";
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max_clk = "800 MHz";
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break;
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case AM3715_1GHZ:
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cpu_family_s = "AM";
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cpu_s = "3715";
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max_clk = "1 GHz";
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break;
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case OMAP3725:
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cpu_family_s = "OMAP";
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cpu_s = "3625/3725";
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max_clk = "800 MHz";
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break;
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case OMAP3725_1GHZ:
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cpu_family_s = "OMAP";
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cpu_s = "3625/3725";
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max_clk = "1 GHz";
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break;
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case OMAP3730:
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cpu_family_s = "OMAP";
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cpu_s = "3630/3730";
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max_clk = "800 MHz";
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break;
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case OMAP3730_1GHZ:
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cpu_family_s = "OMAP";
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cpu_s = "3630/3730";
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max_clk = "1 GHz";
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break;
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default:
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cpu_family_s = "OMAP/AM";
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cpu_s = "36XX/37XX";
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max_clk = "1 GHz";
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break;
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}
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break;
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default:
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cpu_family_s = "OMAP";
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cpu_s = "35XX";
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max_clk = "600 MHz";
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}
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switch (get_device_type()) {
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case TST_DEVICE:
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sec_s = "TST";
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break;
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case EMU_DEVICE:
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sec_s = "EMU";
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break;
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case HS_DEVICE:
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sec_s = "HS";
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break;
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case GP_DEVICE:
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sec_s = "GP";
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break;
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default:
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sec_s = "?";
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}
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if (CPU_OMAP36XX == get_cpu_family())
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printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n",
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cpu_family_s, cpu_s, sec_s,
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rev_s_37xx[get_cpu_rev()], max_clk);
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else
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printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
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cpu_family_s, cpu_s, sec_s,
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rev_s[get_cpu_rev()], max_clk);
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return 0;
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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