219 lines
3.2 KiB
C
219 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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/*
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* CPU test
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* Store instructions: stb(x)(u), sth(x)(u), stw(x)(u)
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*
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* All operations are performed on a 16-byte array. The array
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* is 4-byte aligned. The base register points to offset 8.
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* The immediate offset (index register) ranges in [-8 ... +7].
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* The test cases are composed so that they do not
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* cause alignment exceptions.
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* The test contains a pre-built table describing all test cases.
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* The table entry contains:
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* the instruction opcode, the value of the index register and
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* the value of the source register. After executing the
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* instruction, the test verifies the contents of the array
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* and the value of the base register (it must change for "store
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* with update" instructions).
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*/
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#include <post.h>
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#include "cpu_asm.h"
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#if CONFIG_POST & CONFIG_SYS_POST_CPU
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extern void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3);
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extern void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2);
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static struct cpu_post_store_s
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{
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ulong cmd;
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uint width;
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int update;
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int index;
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ulong offset;
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ulong value;
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} cpu_post_store_table[] =
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{
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{
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OP_STW,
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4,
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0,
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0,
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-4,
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0xff00ff00
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},
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{
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OP_STH,
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2,
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0,
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0,
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-2,
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0xff00
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},
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{
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OP_STB,
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1,
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0,
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0,
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-1,
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0xff
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},
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{
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OP_STWU,
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4,
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1,
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0,
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-4,
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0xff00ff00
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},
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{
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OP_STHU,
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2,
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1,
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0,
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-2,
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0xff00
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},
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{
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OP_STBU,
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1,
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1,
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0,
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-1,
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0xff
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},
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{
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OP_STWX,
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4,
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0,
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1,
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-4,
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0xff00ff00
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},
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{
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OP_STHX,
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2,
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0,
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1,
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-2,
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0xff00
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},
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{
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OP_STBX,
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1,
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0,
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1,
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-1,
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0xff
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},
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{
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OP_STWUX,
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4,
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1,
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1,
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-4,
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0xff00ff00
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},
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{
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OP_STHUX,
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2,
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1,
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1,
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-2,
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0xff00
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},
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{
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OP_STBUX,
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1,
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1,
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1,
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-1,
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0xff
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},
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};
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static unsigned int cpu_post_store_size = ARRAY_SIZE(cpu_post_store_table);
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int cpu_post_test_store (void)
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{
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int ret = 0;
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unsigned int i;
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int flag = disable_interrupts();
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for (i = 0; i < cpu_post_store_size && ret == 0; i++)
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{
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struct cpu_post_store_s *test = cpu_post_store_table + i;
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uchar data[16] =
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{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
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ulong base0 = (ulong) (data + 8);
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ulong base = base0;
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if (test->index)
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{
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ulong code[] =
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{
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ASM_12(test->cmd, 5, 3, 4),
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ASM_BLR,
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};
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cpu_post_exec_12w (code, &base, test->offset, test->value);
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}
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else
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{
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ulong code[] =
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{
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ASM_11I(test->cmd, 4, 3, test->offset),
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ASM_BLR,
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};
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cpu_post_exec_11w (code, &base, test->value);
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}
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if (ret == 0)
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{
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if (test->update)
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ret = base == base0 + test->offset ? 0 : -1;
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else
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ret = base == base0 ? 0 : -1;
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}
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if (ret == 0)
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{
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switch (test->width)
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{
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case 1:
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ret = *(uchar *)(base0 + test->offset) == test->value ?
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0 : -1;
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break;
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case 2:
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ret = *(ushort *)(base0 + test->offset) == test->value ?
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0 : -1;
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break;
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case 4:
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ret = *(ulong *)(base0 + test->offset) == test->value ?
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0 : -1;
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break;
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}
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}
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if (ret != 0)
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{
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post_log ("Error at store test %d !\n", i);
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}
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}
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if (flag)
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enable_interrupts();
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return ret;
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}
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#endif
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