742 lines
16 KiB
C
742 lines
16 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <i2c.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "ddr3_init.h"
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#define A38X_NUMBER_OF_INTERFACES 5
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#define SAR_DEV_ID_OFFS 27
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#define SAR_DEV_ID_MASK 0x7
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/* Termal Sensor Registers */
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#define TSEN_STATE_REG 0xe4070
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#define TSEN_STATE_OFFSET 31
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#define TSEN_STATE_MASK (0x1 << TSEN_STATE_OFFSET)
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#define TSEN_CONF_REG 0xe4074
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#define TSEN_CONF_RST_OFFSET 8
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#define TSEN_CONF_RST_MASK (0x1 << TSEN_CONF_RST_OFFSET)
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#define TSEN_STATUS_REG 0xe4078
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#define TSEN_STATUS_READOUT_VALID_OFFSET 10
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#define TSEN_STATUS_READOUT_VALID_MASK (0x1 << \
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TSEN_STATUS_READOUT_VALID_OFFSET)
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#define TSEN_STATUS_TEMP_OUT_OFFSET 0
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#define TSEN_STATUS_TEMP_OUT_MASK (0x3ff << TSEN_STATUS_TEMP_OUT_OFFSET)
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static struct dfx_access interface_map[] = {
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/* Pipe Client */
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{ 0, 17 },
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{ 1, 7 },
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{ 1, 11 },
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{ 0, 3 },
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{ 1, 25 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 }
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};
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/* This array hold the board round trip delay (DQ and CK) per <interface,bus> */
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struct trip_delay_element a38x_board_round_trip_delay_array[] = {
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/* 1st board */
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/* Interface bus DQS-delay CK-delay */
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{ 3952, 5060 },
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{ 3192, 4493 },
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{ 4785, 6677 },
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{ 3413, 7267 },
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{ 4282, 6086 }, /* ECC PUP */
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{ 3952, 5134 },
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{ 3192, 4567 },
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{ 4785, 6751 },
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{ 3413, 7341 },
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{ 4282, 6160 }, /* ECC PUP */
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/* 2nd board */
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/* Interface bus DQS-delay CK-delay */
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{ 3952, 5060 },
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{ 3192, 4493 },
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{ 4785, 6677 },
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{ 3413, 7267 },
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{ 4282, 6086 }, /* ECC PUP */
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{ 3952, 5134 },
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{ 3192, 4567 },
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{ 4785, 6751 },
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{ 3413, 7341 },
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{ 4282, 6160 } /* ECC PUP */
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};
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#ifdef STATIC_ALGO_SUPPORT
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/* package trace */
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static struct trip_delay_element a38x_package_round_trip_delay_array[] = {
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/* IF BUS DQ_DELAY CK_DELAY */
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 },
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{ 0, 0 }
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};
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static int a38x_silicon_delay_offset[] = {
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/* board 0 */
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0,
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/* board 1 */
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0,
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/* board 2 */
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0
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};
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#endif
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static u8 a38x_bw_per_freq[DDR_FREQ_LIMIT] = {
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0x3, /* DDR_FREQ_100 */
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0x4, /* DDR_FREQ_400 */
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0x4, /* DDR_FREQ_533 */
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0x5, /* DDR_FREQ_667 */
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0x5, /* DDR_FREQ_800 */
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0x5, /* DDR_FREQ_933 */
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0x5, /* DDR_FREQ_1066 */
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0x3, /* DDR_FREQ_311 */
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0x3, /* DDR_FREQ_333 */
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0x4, /* DDR_FREQ_467 */
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0x5, /* DDR_FREQ_850 */
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0x5, /* DDR_FREQ_600 */
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0x3, /* DDR_FREQ_300 */
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0x5, /* DDR_FREQ_900 */
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0x3, /* DDR_FREQ_360 */
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0x5 /* DDR_FREQ_1000 */
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};
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static u8 a38x_rate_per_freq[DDR_FREQ_LIMIT] = {
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/*TBD*/ 0x1, /* DDR_FREQ_100 */
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0x2, /* DDR_FREQ_400 */
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0x2, /* DDR_FREQ_533 */
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0x2, /* DDR_FREQ_667 */
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0x2, /* DDR_FREQ_800 */
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0x3, /* DDR_FREQ_933 */
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0x3, /* DDR_FREQ_1066 */
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0x1, /* DDR_FREQ_311 */
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0x1, /* DDR_FREQ_333 */
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0x2, /* DDR_FREQ_467 */
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0x2, /* DDR_FREQ_850 */
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0x2, /* DDR_FREQ_600 */
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0x1, /* DDR_FREQ_300 */
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0x2, /* DDR_FREQ_900 */
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0x1, /* DDR_FREQ_360 */
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0x2 /* DDR_FREQ_1000 */
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};
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static u16 a38x_vco_freq_per_sar[] = {
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666, /* 0 */
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1332,
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800,
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1600,
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1066,
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2132,
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1200,
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2400,
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1332,
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1332,
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1500,
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1500,
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1600, /* 12 */
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1600,
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1700,
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1700,
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1866,
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1866,
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1800, /* 18 */
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2000,
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2000,
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4000,
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2132,
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2132,
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2300,
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2300,
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2400,
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2400,
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2500,
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2500,
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800
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};
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u32 pipe_multicast_mask;
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u32 dq_bit_map_2_phy_pin[] = {
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1, 0, 2, 6, 9, 8, 3, 7, /* 0 */
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8, 9, 1, 7, 2, 6, 3, 0, /* 1 */
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3, 9, 7, 8, 1, 0, 2, 6, /* 2 */
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1, 0, 6, 2, 8, 3, 7, 9, /* 3 */
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0, 1, 2, 9, 7, 8, 3, 6, /* 4 */
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};
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static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
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enum hws_ddr_freq freq);
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/*
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* Read temperature TJ value
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*/
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u32 ddr3_ctrl_get_junc_temp(u8 dev_num)
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{
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int reg = 0;
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/* Initiates TSEN hardware reset once */
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if ((reg_read(TSEN_CONF_REG) & TSEN_CONF_RST_MASK) == 0)
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reg_bit_set(TSEN_CONF_REG, TSEN_CONF_RST_MASK);
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mdelay(10);
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/* Check if the readout field is valid */
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if ((reg_read(TSEN_STATUS_REG) & TSEN_STATUS_READOUT_VALID_MASK) == 0) {
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printf("%s: TSEN not ready\n", __func__);
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return 0;
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}
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reg = reg_read(TSEN_STATUS_REG);
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reg = (reg & TSEN_STATUS_TEMP_OUT_MASK) >> TSEN_STATUS_TEMP_OUT_OFFSET;
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return ((((10000 * reg) / 21445) * 1000) - 272674) / 1000;
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}
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/*
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* Name: ddr3_tip_a38x_get_freq_config.
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* Desc:
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* Args:
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* Notes:
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* Returns: MV_OK if success, other error code if fail.
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*/
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int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq,
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struct hws_tip_freq_config_info
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*freq_config_info)
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{
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if (a38x_bw_per_freq[freq] == 0xff)
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return MV_NOT_SUPPORTED;
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if (freq_config_info == NULL)
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return MV_BAD_PARAM;
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freq_config_info->bw_per_freq = a38x_bw_per_freq[freq];
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freq_config_info->rate_per_freq = a38x_rate_per_freq[freq];
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freq_config_info->is_supported = 1;
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return MV_OK;
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}
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/*
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* Name: ddr3_tip_a38x_pipe_enable.
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* Desc:
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* Args:
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* Notes:
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* Returns: MV_OK if success, other error code if fail.
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*/
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int ddr3_tip_a38x_pipe_enable(u8 dev_num, enum hws_access_type interface_access,
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u32 if_id, int enable)
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{
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u32 data_value, pipe_enable_mask = 0;
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if (enable == 0) {
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pipe_enable_mask = 0;
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} else {
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if (interface_access == ACCESS_TYPE_MULTICAST)
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pipe_enable_mask = pipe_multicast_mask;
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else
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pipe_enable_mask = (1 << interface_map[if_id].pipe);
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}
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CHECK_STATUS(ddr3_tip_reg_read
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(dev_num, PIPE_ENABLE_ADDR, &data_value, MASK_ALL_BITS));
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data_value = (data_value & (~0xff)) | pipe_enable_mask;
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CHECK_STATUS(ddr3_tip_reg_write(dev_num, PIPE_ENABLE_ADDR, data_value));
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return MV_OK;
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}
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/*
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* Name: ddr3_tip_a38x_if_write.
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* Desc:
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* Args:
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* Notes:
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* Returns: MV_OK if success, other error code if fail.
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*/
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int ddr3_tip_a38x_if_write(u8 dev_num, enum hws_access_type interface_access,
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u32 if_id, u32 reg_addr, u32 data_value,
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u32 mask)
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{
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u32 ui_data_read;
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if (mask != MASK_ALL_BITS) {
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CHECK_STATUS(ddr3_tip_a38x_if_read
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(dev_num, ACCESS_TYPE_UNICAST, if_id, reg_addr,
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&ui_data_read, MASK_ALL_BITS));
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data_value = (ui_data_read & (~mask)) | (data_value & mask);
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}
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reg_write(reg_addr, data_value);
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return MV_OK;
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}
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/*
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* Name: ddr3_tip_a38x_if_read.
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* Desc:
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* Args:
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* Notes:
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* Returns: MV_OK if success, other error code if fail.
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*/
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int ddr3_tip_a38x_if_read(u8 dev_num, enum hws_access_type interface_access,
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u32 if_id, u32 reg_addr, u32 *data, u32 mask)
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{
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*data = reg_read(reg_addr) & mask;
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return MV_OK;
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}
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/*
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* Name: ddr3_tip_a38x_select_ddr_controller.
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* Desc: Enable/Disable access to Marvell's server.
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* Args: dev_num - device number
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* enable - whether to enable or disable the server
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* Notes:
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* Returns: MV_OK if success, other error code if fail.
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*/
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int ddr3_tip_a38x_select_ddr_controller(u8 dev_num, int enable)
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{
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u32 reg;
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reg = reg_read(CS_ENABLE_REG);
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if (enable)
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reg |= (1 << 6);
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else
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reg &= ~(1 << 6);
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reg_write(CS_ENABLE_REG, reg);
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return MV_OK;
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}
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/*
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* Name: ddr3_tip_init_a38x_silicon.
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* Desc: init Training SW DB.
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* Args:
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* Notes:
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* Returns: MV_OK if success, other error code if fail.
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*/
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static int ddr3_tip_init_a38x_silicon(u32 dev_num, u32 board_id)
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{
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struct hws_tip_config_func_db config_func;
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enum hws_ddr_freq ddr_freq;
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int status;
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struct hws_topology_map *tm = ddr3_get_topology_map();
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/* new read leveling version */
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config_func.tip_dunit_read_func = ddr3_tip_a38x_if_read;
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config_func.tip_dunit_write_func = ddr3_tip_a38x_if_write;
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config_func.tip_dunit_mux_select_func =
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ddr3_tip_a38x_select_ddr_controller;
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config_func.tip_get_freq_config_info_func =
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ddr3_tip_a38x_get_freq_config;
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config_func.tip_set_freq_divider_func = ddr3_tip_a38x_set_divider;
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config_func.tip_get_device_info_func = ddr3_tip_a38x_get_device_info;
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config_func.tip_get_temperature = ddr3_ctrl_get_junc_temp;
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ddr3_tip_init_config_func(dev_num, &config_func);
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ddr3_tip_register_dq_table(dev_num, dq_bit_map_2_phy_pin);
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#ifdef STATIC_ALGO_SUPPORT
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{
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struct hws_tip_static_config_info static_config;
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u32 board_offset =
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board_id * A38X_NUMBER_OF_INTERFACES *
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tm->num_of_bus_per_interface;
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static_config.silicon_delay =
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a38x_silicon_delay_offset[board_id];
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static_config.package_trace_arr =
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a38x_package_round_trip_delay_array;
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static_config.board_trace_arr =
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&a38x_board_round_trip_delay_array[board_offset];
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ddr3_tip_init_static_config_db(dev_num, &static_config);
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}
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#endif
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status = ddr3_tip_a38x_get_init_freq(dev_num, &ddr_freq);
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if (MV_OK != status) {
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DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
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("DDR3 silicon get target frequency - FAILED 0x%x\n",
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status));
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return status;
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}
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rl_version = 1;
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mask_tune_func = (SET_LOW_FREQ_MASK_BIT |
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LOAD_PATTERN_MASK_BIT |
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SET_MEDIUM_FREQ_MASK_BIT | WRITE_LEVELING_MASK_BIT |
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/* LOAD_PATTERN_2_MASK_BIT | */
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WRITE_LEVELING_SUPP_MASK_BIT |
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READ_LEVELING_MASK_BIT |
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PBS_RX_MASK_BIT |
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PBS_TX_MASK_BIT |
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SET_TARGET_FREQ_MASK_BIT |
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WRITE_LEVELING_TF_MASK_BIT |
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WRITE_LEVELING_SUPP_TF_MASK_BIT |
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READ_LEVELING_TF_MASK_BIT |
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CENTRALIZATION_RX_MASK_BIT |
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CENTRALIZATION_TX_MASK_BIT);
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rl_mid_freq_wa = 1;
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if ((ddr_freq == DDR_FREQ_333) || (ddr_freq == DDR_FREQ_400)) {
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mask_tune_func = (WRITE_LEVELING_MASK_BIT |
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LOAD_PATTERN_2_MASK_BIT |
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WRITE_LEVELING_SUPP_MASK_BIT |
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READ_LEVELING_MASK_BIT |
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PBS_RX_MASK_BIT |
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PBS_TX_MASK_BIT |
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CENTRALIZATION_RX_MASK_BIT |
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CENTRALIZATION_TX_MASK_BIT);
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rl_mid_freq_wa = 0; /* WA not needed if 333/400 is TF */
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}
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/* Supplementary not supported for ECC modes */
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if (1 == ddr3_if_ecc_enabled()) {
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mask_tune_func &= ~WRITE_LEVELING_SUPP_TF_MASK_BIT;
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mask_tune_func &= ~WRITE_LEVELING_SUPP_MASK_BIT;
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mask_tune_func &= ~PBS_TX_MASK_BIT;
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mask_tune_func &= ~PBS_RX_MASK_BIT;
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}
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if (ck_delay == -1)
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ck_delay = 160;
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if (ck_delay_16 == -1)
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ck_delay_16 = 160;
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ca_delay = 0;
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delay_enable = 1;
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calibration_update_control = 1;
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init_freq = tm->interface_params[first_active_if].memory_freq;
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ddr3_tip_a38x_get_medium_freq(dev_num, &medium_freq);
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return MV_OK;
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}
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int ddr3_a38x_update_topology_map(u32 dev_num, struct hws_topology_map *tm)
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{
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u32 if_id = 0;
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enum hws_ddr_freq freq;
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ddr3_tip_a38x_get_init_freq(dev_num, &freq);
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tm->interface_params[if_id].memory_freq = freq;
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/*
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* re-calc topology parameters according to topology updates
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* (if needed)
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*/
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CHECK_STATUS(hws_ddr3_tip_load_topology_map(dev_num, tm));
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return MV_OK;
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}
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int ddr3_tip_init_a38x(u32 dev_num, u32 board_id)
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{
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struct hws_topology_map *tm = ddr3_get_topology_map();
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if (NULL == tm)
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return MV_FAIL;
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ddr3_a38x_update_topology_map(dev_num, tm);
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ddr3_tip_init_a38x_silicon(dev_num, board_id);
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return MV_OK;
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}
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int ddr3_tip_a38x_get_init_freq(int dev_num, enum hws_ddr_freq *freq)
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{
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u32 reg;
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/* Read sample at reset setting */
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reg = (reg_read(REG_DEVICE_SAR1_ADDR) >>
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RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) &
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RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
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switch (reg) {
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case 0x0:
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case 0x1:
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*freq = DDR_FREQ_333;
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break;
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case 0x2:
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case 0x3:
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*freq = DDR_FREQ_400;
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break;
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case 0x4:
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case 0xd:
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*freq = DDR_FREQ_533;
|
|
break;
|
|
case 0x6:
|
|
*freq = DDR_FREQ_600;
|
|
break;
|
|
case 0x8:
|
|
case 0x11:
|
|
case 0x14:
|
|
*freq = DDR_FREQ_667;
|
|
break;
|
|
case 0xc:
|
|
case 0x15:
|
|
case 0x1b:
|
|
*freq = DDR_FREQ_800;
|
|
break;
|
|
case 0x10:
|
|
*freq = DDR_FREQ_933;
|
|
break;
|
|
case 0x12:
|
|
*freq = DDR_FREQ_900;
|
|
break;
|
|
case 0x13:
|
|
*freq = DDR_FREQ_900;
|
|
break;
|
|
default:
|
|
*freq = 0;
|
|
return MV_NOT_SUPPORTED;
|
|
}
|
|
|
|
return MV_OK;
|
|
}
|
|
|
|
int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq)
|
|
{
|
|
u32 reg;
|
|
|
|
/* Read sample at reset setting */
|
|
reg = (reg_read(REG_DEVICE_SAR1_ADDR) >>
|
|
RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) &
|
|
RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
|
|
switch (reg) {
|
|
case 0x0:
|
|
case 0x1:
|
|
/* Medium is same as TF to run PBS in this freq */
|
|
*freq = DDR_FREQ_333;
|
|
break;
|
|
case 0x2:
|
|
case 0x3:
|
|
/* Medium is same as TF to run PBS in this freq */
|
|
*freq = DDR_FREQ_400;
|
|
break;
|
|
case 0x4:
|
|
case 0xd:
|
|
*freq = DDR_FREQ_533;
|
|
break;
|
|
case 0x8:
|
|
case 0x11:
|
|
case 0x14:
|
|
*freq = DDR_FREQ_333;
|
|
break;
|
|
case 0xc:
|
|
case 0x15:
|
|
case 0x1b:
|
|
*freq = DDR_FREQ_400;
|
|
break;
|
|
case 0x6:
|
|
*freq = DDR_FREQ_300;
|
|
break;
|
|
case 0x12:
|
|
*freq = DDR_FREQ_360;
|
|
break;
|
|
case 0x13:
|
|
*freq = DDR_FREQ_400;
|
|
break;
|
|
default:
|
|
*freq = 0;
|
|
return MV_NOT_SUPPORTED;
|
|
}
|
|
|
|
return MV_OK;
|
|
}
|
|
|
|
u32 ddr3_tip_get_init_freq(void)
|
|
{
|
|
enum hws_ddr_freq freq;
|
|
|
|
ddr3_tip_a38x_get_init_freq(0, &freq);
|
|
|
|
return freq;
|
|
}
|
|
|
|
static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
|
|
enum hws_ddr_freq frequency)
|
|
{
|
|
u32 divider = 0;
|
|
u32 sar_val;
|
|
|
|
if (if_id != 0) {
|
|
DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
|
|
("A38x does not support interface 0x%x\n",
|
|
if_id));
|
|
return MV_BAD_PARAM;
|
|
}
|
|
|
|
/* get VCO freq index */
|
|
sar_val = (reg_read(REG_DEVICE_SAR1_ADDR) >>
|
|
RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) &
|
|
RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
|
|
divider = a38x_vco_freq_per_sar[sar_val] / freq_val[frequency];
|
|
|
|
/* Set Sync mode */
|
|
CHECK_STATUS(ddr3_tip_a38x_if_write
|
|
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0x20220, 0x0,
|
|
0x1000));
|
|
CHECK_STATUS(ddr3_tip_a38x_if_write
|
|
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe42f4, 0x0,
|
|
0x200));
|
|
|
|
/* cpupll_clkdiv_reset_mask */
|
|
CHECK_STATUS(ddr3_tip_a38x_if_write
|
|
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0x1f,
|
|
0xff));
|
|
|
|
/* cpupll_clkdiv_reload_smooth */
|
|
CHECK_STATUS(ddr3_tip_a38x_if_write
|
|
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260,
|
|
(0x2 << 8), (0xff << 8)));
|
|
|
|
/* cpupll_clkdiv_relax_en */
|
|
CHECK_STATUS(ddr3_tip_a38x_if_write
|
|
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260,
|
|
(0x2 << 24), (0xff << 24)));
|
|
|
|
/* write the divider */
|
|
CHECK_STATUS(ddr3_tip_a38x_if_write
|
|
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4268,
|
|
(divider << 8), (0x3f << 8)));
|
|
|
|
/* set cpupll_clkdiv_reload_ratio */
|
|
CHECK_STATUS(ddr3_tip_a38x_if_write
|
|
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264,
|
|
(1 << 8), (1 << 8)));
|
|
|
|
/* undet cpupll_clkdiv_reload_ratio */
|
|
CHECK_STATUS(ddr3_tip_a38x_if_write
|
|
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0,
|
|
(1 << 8)));
|
|
|
|
/* clear cpupll_clkdiv_reload_force */
|
|
CHECK_STATUS(ddr3_tip_a38x_if_write
|
|
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, 0,
|
|
(0xff << 8)));
|
|
|
|
/* clear cpupll_clkdiv_relax_en */
|
|
CHECK_STATUS(ddr3_tip_a38x_if_write
|
|
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, 0,
|
|
(0xff << 24)));
|
|
|
|
/* clear cpupll_clkdiv_reset_mask */
|
|
CHECK_STATUS(ddr3_tip_a38x_if_write
|
|
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0,
|
|
0xff));
|
|
|
|
/* Dunit training clock + 1:1 mode */
|
|
if ((frequency == DDR_FREQ_LOW_FREQ) || (freq_val[frequency] <= 400)) {
|
|
CHECK_STATUS(ddr3_tip_a38x_if_write
|
|
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0x18488,
|
|
(1 << 16), (1 << 16)));
|
|
CHECK_STATUS(ddr3_tip_a38x_if_write
|
|
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1524,
|
|
(0 << 15), (1 << 15)));
|
|
} else {
|
|
CHECK_STATUS(ddr3_tip_a38x_if_write
|
|
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0x18488,
|
|
0, (1 << 16)));
|
|
CHECK_STATUS(ddr3_tip_a38x_if_write
|
|
(dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1524,
|
|
(1 << 15), (1 << 15)));
|
|
}
|
|
|
|
return MV_OK;
|
|
}
|
|
|
|
/*
|
|
* external read from memory
|
|
*/
|
|
int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
|
|
u32 num_of_bursts, u32 *data)
|
|
{
|
|
u32 burst_num;
|
|
|
|
for (burst_num = 0; burst_num < num_of_bursts * 8; burst_num++)
|
|
data[burst_num] = readl(reg_addr + 4 * burst_num);
|
|
|
|
return MV_OK;
|
|
}
|
|
|
|
/*
|
|
* external write to memory
|
|
*/
|
|
int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
|
|
u32 num_of_bursts, u32 *data) {
|
|
u32 burst_num;
|
|
|
|
for (burst_num = 0; burst_num < num_of_bursts * 8; burst_num++)
|
|
writel(data[burst_num], reg_addr + 4 * burst_num);
|
|
|
|
return MV_OK;
|
|
}
|
|
|
|
int ddr3_silicon_pre_init(void)
|
|
{
|
|
int result;
|
|
|
|
result = ddr3_silicon_init();
|
|
|
|
return result;
|
|
}
|
|
|
|
int ddr3_post_run_alg(void)
|
|
{
|
|
return MV_OK;
|
|
}
|
|
|
|
int ddr3_silicon_post_init(void)
|
|
{
|
|
struct hws_topology_map *tm = ddr3_get_topology_map();
|
|
|
|
/* Set half bus width */
|
|
if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask)) {
|
|
CHECK_STATUS(ddr3_tip_if_write
|
|
(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
|
|
REG_SDRAM_CONFIG_ADDR, 0x0, 0x8000));
|
|
}
|
|
|
|
return MV_OK;
|
|
}
|
|
|
|
int ddr3_tip_a38x_get_device_info(u8 dev_num, struct ddr3_device_info *info_ptr)
|
|
{
|
|
info_ptr->device_id = 0x6800;
|
|
info_ptr->ck_delay = ck_delay;
|
|
|
|
return MV_OK;
|
|
}
|