289 lines
12 KiB
C
289 lines
12 KiB
C
/*
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* mux.c
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include "board.h"
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static struct module_pin_mux uart2_pin_mux[] = {
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{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
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{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
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{-1},
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};
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static struct module_pin_mux uart3_pin_mux[] = {
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{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
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{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
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{-1},
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};
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static struct module_pin_mux uart4_pin_mux[] = {
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{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
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{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
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{-1},
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};
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static struct module_pin_mux uart5_pin_mux[] = {
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{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
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{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
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{-1},
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};
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static struct module_pin_mux i2c0_pin_mux[] = {
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
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PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* I2C_DATA */
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
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PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* I2C_SCLK */
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{-1},
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};
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#ifdef CONFIG_NAND
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static struct module_pin_mux nand_pin_mux[] = {
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{OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
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{OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
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{OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
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{OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
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{OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
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{OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
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{OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
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{OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
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#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
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{OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
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{OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
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{OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
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{OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
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{OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
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{OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
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{OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
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{OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
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#endif
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{OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
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{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */
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{OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */
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{OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */
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{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
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{-1},
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};
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#elif defined(CONFIG_NOR)
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static struct module_pin_mux bone_norcape_pin_mux[] = {
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{OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */
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{OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */
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{OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */
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{OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */
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{OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */
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{OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */
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{OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */
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{OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */
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{OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */
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{OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */
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{OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */
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{OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */
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{OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */
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{OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */
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{OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */
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{OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */
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{OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */
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{OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */
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{OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */
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{OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */
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{OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */
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{OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */
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{OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */
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{OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */
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{OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */
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{OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
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{OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
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{OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
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{OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */
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{OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
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{-1},
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};
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#endif
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static struct module_pin_mux uart0_netbird_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN)}, /* UART0_TXD */
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{-1},
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};
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static struct module_pin_mux uart1_netbird_pin_mux[] = {
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{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (D16) uart1_rxd.uart1_rxd */
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{OFFSET(uart1_txd), (MODE(0) | PULLUDEN | PULLUP_EN)}, /* (D15) uart1_txd.uart1_txd */
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{OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (D18) uart1_ctsn.uart1_ctsn */
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{OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN | PULLUP_EN)}, /* (D17) uart1_rtsn.uart1_rtsn */
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{-1},
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};
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static struct module_pin_mux rmii0_netbird_pin_mux[] = {
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{OFFSET(mii1_crs), MODE(1) | PULLUDDIS | RXACTIVE}, /* MII1_CRS */
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{OFFSET(mii1_rxerr), MODE(1) | PULLUDDIS | RXACTIVE}, /* MII1_RXERR */
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{OFFSET(mii1_txen), MODE(1) | PULLUDDIS }, /* MII1_TXEN */
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{OFFSET(mii1_txd0), MODE(1) | PULLUDDIS }, /* MII1_TXD0 */
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{OFFSET(mii1_txd1), MODE(1) | PULLUDDIS }, /* MII1_TXD1 */
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{OFFSET(mii1_rxd0), MODE(1) | PULLUDDIS | RXACTIVE }, /* MII1_RXD0 */
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{OFFSET(mii1_rxd1), MODE(1) | PULLUDDIS | RXACTIVE }, /* MII1_RXD1 */
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{OFFSET(rmii1_refclk), MODE(0) | PULLUDDIS | RXACTIVE}, /* RMII1_REFCLK */
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{OFFSET(mdio_clk), MODE(0) | PULLUDDIS }, /* MDIO_CLK */
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{OFFSET(mdio_data), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE }, /* MDIO_DATA */
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{-1},
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};
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static struct module_pin_mux rmii1_netbird_pin_mux[] = {
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{OFFSET(gpmc_a9), MODE(3) | PULLUDDIS | RXACTIVE}, /* MII2_CRS */
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{OFFSET(gpmc_wpn), MODE(3) | PULLUDDIS | RXACTIVE}, /* MII2_RXERR */
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{OFFSET(gpmc_a0), MODE(3) | PULLUDDIS}, /* MII2_TXEN */
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{OFFSET(gpmc_a5), MODE(3) | PULLUDDIS}, /* MII2_TXD0 */
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{OFFSET(gpmc_a4), MODE(3) | PULLUDDIS}, /* MII2_TXD1 */
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{OFFSET(gpmc_a11), MODE(3) | PULLUDDIS | RXACTIVE}, /* MII1_RXD0 */
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{OFFSET(gpmc_a10), MODE(3) | PULLUDDIS | RXACTIVE}, /* MII1_RXD1 */
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{OFFSET(mii1_col), MODE(1) | PULLUDDIS | RXACTIVE}, /* RMII1_REFCLK */
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{-1},
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};
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static struct module_pin_mux mmc0_sdio_netbird_pin_mux[] = {
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{OFFSET(mmc0_clk), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | PULLUDEN | PULLUP_EN)}, /* MMC0_CMD */
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{OFFSET(mmc0_dat0), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT0 */
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{OFFSET(mmc0_dat1), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat2), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat3), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT3 */
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{-1},
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};
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static struct module_pin_mux mmc1_emmc_netbird_pin_mux[] = {
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{OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_CLK */
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{OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_CMD */
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{OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT0 */
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{OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT1 */
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{OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT2 */
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{OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */
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{OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */
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{OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */
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{OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */
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{OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */
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{-1},
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};
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static struct module_pin_mux gpio_netbird_pin_mux[] = {
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/* Bank 0 */
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{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* (C18) eCAP0_in_PWM0_out.gpio0[7] */ /* PWM */
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{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)}, /* (J18) gmii1_txd3.gpio0[16] */ /* RST_PHY~ */
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{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)}, /* (U12) gpmc_ad11.gpio0[27] */ /* RST_EXT~ */
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/* Bank 1 */
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{OFFSET(gpmc_ad13), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (R12) gpmc_ad13.gpio1[13] */ /* BUTTON */
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{OFFSET(gpmc_ad14), (MODE(7) | PULLUDDIS)}, /* (V13) gpmc_ad14.gpio1[14] */ /* LED_A */
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{OFFSET(gpmc_ad15), (MODE(7) | PULLUDDIS)}, /* (U13) gpmc_ad15.gpio1[15] */ /* LED_B */
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{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)}, /* (U15) gpmc_a6.gpio1[22] */ /* GSM_PWR_EN */
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{OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS)}, /* (V16) gpmc_a8.gpio1[24] */ /* RST_GSM~ */
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/* Bank 2 */
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{OFFSET(lcd_pclk), (MODE(7) | PULLUDDIS)}, /* (V5) lcd_pclk.gpio2[24] */ /* EN_GPS_ANT */
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{OFFSET(lcd_data3), (MODE(7) | PULLUDEN| PULLUP_EN)}, /* (V5) lcd_pclk.gpio2[9] */ /* SYSBOOT */
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{OFFSET(lcd_data4), (MODE(7) | PULLUDEN| PULLUP_EN)}, /* (V5) lcd_pclk.gpio2[10] */ /* SYSBOOT */
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/* Bank 3 */
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{OFFSET(mii1_rxdv), (MODE(7) | PULLUDDIS)}, /* (J17) gmii1_rxdv.gpio3[4] */ /* BT_EN */
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{OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (K18) gmii1_txclk.gpio3[9] */ /* WLAN_IRQ */
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{OFFSET(mii1_rxdv), (MODE(7) | PULLUDDIS)}, /* (L18) gmii1_rxclk.gpio3[10] */ /* WLAN_EN */
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{-1},
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};
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static struct module_pin_mux usb_netbird_pin_mux[] = {
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{OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN | PULLDOWN_EN)}, /* (F16) USB0_DRVVBUS.USB0_DRVVBUS */ /* PWM */
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{OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS | PULLDOWN_EN)}, /* (F15) USB1_DRVVBUS.USB1_DRVVBUS */ /* RST_PHY~ */
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{-1},
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};
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#if defined(CONFIG_NOR_BOOT)
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void enable_norboot_pin_mux(void)
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{
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configure_module_pin_mux(bone_norcape_pin_mux);
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}
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#endif
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void enable_uart0_pin_mux(void)
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{
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configure_module_pin_mux(uart0_netbird_pin_mux);
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}
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void enable_uart1_pin_mux(void)
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{
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configure_module_pin_mux(uart1_netbird_pin_mux);
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}
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void enable_uart2_pin_mux(void)
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{
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configure_module_pin_mux(uart2_pin_mux);
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}
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void enable_uart3_pin_mux(void)
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{
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configure_module_pin_mux(uart3_pin_mux);
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}
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void enable_uart4_pin_mux(void)
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{
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configure_module_pin_mux(uart4_pin_mux);
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}
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void enable_uart5_pin_mux(void)
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{
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configure_module_pin_mux(uart5_pin_mux);
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}
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void enable_i2c0_pin_mux(void)
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{
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configure_module_pin_mux(i2c0_pin_mux);
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}
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/*
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* The AM335x GP EVM, if daughter card(s) are connected, can have 8
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* different profiles. These profiles determine what peripherals are
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* valid and need pinmux to be configured.
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*/
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#define PROFILE_NONE 0x0
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#define PROFILE_0 (1 << 0)
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#define PROFILE_1 (1 << 1)
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#define PROFILE_2 (1 << 2)
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#define PROFILE_3 (1 << 3)
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#define PROFILE_4 (1 << 4)
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#define PROFILE_5 (1 << 5)
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#define PROFILE_6 (1 << 6)
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#define PROFILE_7 (1 << 7)
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#define PROFILE_MASK 0x7
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#define PROFILE_ALL 0xFF
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/* CPLD registers */
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#define I2C_CPLD_ADDR 0x35
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#define CFG_REG 0x10
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void enable_board_pin_mux(void)
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{
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/* Netbird board */
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configure_module_pin_mux(gpio_netbird_pin_mux);
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configure_module_pin_mux(rmii0_netbird_pin_mux);
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configure_module_pin_mux(rmii1_netbird_pin_mux);
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configure_module_pin_mux(mmc0_sdio_netbird_pin_mux);
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configure_module_pin_mux(mmc1_emmc_netbird_pin_mux);
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configure_module_pin_mux(usb_netbird_pin_mux);
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configure_module_pin_mux(usb_netbird_pin_mux);
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configure_module_pin_mux(i2c0_pin_mux);
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}
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