304 lines
11 KiB
Plaintext
304 lines
11 KiB
Plaintext
#
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# Copyright (C) 2014, Simon Glass <sjg@chromium.org>
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# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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U-Boot on x86
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=============
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This document describes the information about U-Boot running on x86 targets,
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including supported boards, build instructions, todo list, etc.
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Status
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------
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U-Boot supports running as a coreboot [1] payload on x86. So far only Link
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(Chromebook Pixel) has been tested, but it should work with minimal adjustments
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on other x86 boards since coreboot deals with most of the low-level details.
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U-Boot also supports booting directly from x86 reset vector without coreboot,
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aka raw support or bare support. Currently Link, Intel Crown Bay, Intel
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Minnowboard Max and Intel Galileo support running U-Boot 'bare metal'.
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As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
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Linux kernel as part of a FIT image. It also supports a compressed zImage.
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Build Instructions
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------------------
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Building U-Boot as a coreboot payload is just like building U-Boot for targets
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on other architectures, like below:
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$ make coreboot-x86_defconfig
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$ make all
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Note this default configuration will build a U-Boot payload for the Link board.
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To build a coreboot payload against another board, you can change the build
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configuration during the 'make menuconfig' process.
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x86 architecture --->
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...
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(chromebook_link) Board configuration file
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(chromebook_link) Board Device Tree Source (dts) file
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(0x19200000) Board specific Cache-As-RAM (CAR) address
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(0x4000) Board specific Cache-As-RAM (CAR) size
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Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
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to point to a new board. You can also change the Cache-As-RAM (CAR) related
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settings here if the default values do not fit your new board.
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Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
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little bit tricky, as generally it requires several binary blobs which are not
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shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
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not turned on by default in the U-Boot source tree. Firstly, you need turn it
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on by enabling the ROM build:
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$ export BUILD_ROM=y
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This tells the Makefile to build u-boot.rom as a target.
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Link-specific instructions:
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First, you need the following binary blobs:
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* descriptor.bin - Intel flash descriptor
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* me.bin - Intel Management Engine
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* mrc.bin - Memory Reference Code, which sets up SDRAM
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* video ROM - sets up the display
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You can get these binary blobs by:
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$ git clone http://review.coreboot.org/p/blobs.git
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$ cd blobs
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Find the following files:
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* ./mainboard/google/link/descriptor.bin
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* ./mainboard/google/link/me.bin
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* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin
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The 3rd one should be renamed to mrc.bin.
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As for the video ROM, you can get it here [2].
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Make sure all these binary blobs are put in the board directory.
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Now you can build U-Boot and obtain u-boot.rom:
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$ make chromebook_link_defconfig
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$ make all
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Intel Crown Bay specific instructions:
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U-Boot support of Intel Crown Bay board [3] relies on a binary blob called
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Firmware Support Package [4] to perform all the necessary initialization steps
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as documented in the BIOS Writer Guide, including initialization of the CPU,
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memory controller, chipset and certain bus interfaces.
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Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
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install it on your host and locate the FSP binary blob. Note this platform
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also requires a Chipset Micro Code (CMC) state machine binary to be present in
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the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
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in this FSP package too.
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* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
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* ./Microcode/C0_22211.BIN
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Rename the first one to fsp.bin and second one to cmc.bin and put them in the
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board directory.
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Note the FSP release version 001 has a bug which could cause random endless
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loop during the FspInit call. This bug was published by Intel although Intel
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did not describe any details. We need manually apply the patch to the FSP
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binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
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binary, change the following five bytes values from orginally E8 42 FF FF FF
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to B8 00 80 0B 00.
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Now you can build U-Boot and obtain u-boot.rom
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$ make crownbay_defconfig
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$ make all
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Intel Minnowboard Max instructions:
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This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
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Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
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the time of writing). Put it in the board directory:
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board/intel/minnowmax/fsp.bin
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Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
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directory: board/intel/minnowmax/vga.bin
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You still need two more binary blobs. These come from the sample SPI image
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provided in the FSP (SPI.bin at the time of writing).
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Use ifdtool in the U-Boot tools directory to extract the images from that
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file, for example:
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$ ./tools/ifdtool -x BayleyBay/SPI.bin
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$ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin
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$ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
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Now you can build U-Boot and obtain u-boot.rom
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$ make minnowmax_defconfig
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$ make all
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Intel Galileo instructions:
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Only one binary blob is needed for Remote Management Unit (RMU) within Intel
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Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is
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needed by the Quark SoC itself.
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You can get the binary blob from Quark Board Support Package from Intel website:
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* ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin
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Rename the file and put it to the board directory by:
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$ cp RMU.bin board/intel/galileo/rmu.bin
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Now you can build U-Boot and obtain u-boot.rom
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$ make galileo_defconfig
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$ make all
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Test with coreboot
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------------------
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For testing U-Boot as the coreboot payload, there are things that need be paid
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attention to. coreboot supports loading an ELF executable and a 32-bit plain
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binary, as well as other supported payloads. With the default configuration,
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U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the
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generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool
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provided by coreboot) manually as coreboot's 'make menuconfig' does not provide
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this capability yet. The command is as follows:
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# in the coreboot root directory
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$ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
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-f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015
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Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the
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symbol address of _start (in arch/x86/cpu/start.S).
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If you want to use ELF as the coreboot payload, change U-Boot configuration to
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use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
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To enable video you must enable these options in coreboot:
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- Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
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- Keep VESA framebuffer
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At present it seems that for Minnowboard Max, coreboot does not pass through
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the video information correctly (it always says the resolution is 0x0). This
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works correctly for link though.
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CPU Microcode
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-------------
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Modern CPUs usually require a special bit stream called microcode [5] to be
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loaded on the processor after power up in order to function properly. U-Boot
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has already integrated these as hex dumps in the source tree.
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Driver Model
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------------
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x86 has been converted to use driver model for serial and GPIO.
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Device Tree
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-----------
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x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
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be turned on. Not every device on the board is configured via device tree, but
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more and more devices will be added as time goes by. Check out the directory
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arch/x86/dts/ for these device tree source files.
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Useful Commands
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---------------
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In keeping with the U-Boot philosophy of providing functions to check and
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adjust internal settings, there are several x86-specific commands that may be
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useful:
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hob - Display information about Firmware Support Package (FSP) Hand-off
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Block. This is only available on platforms which use FSP, mostly
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Atom.
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iod - Display I/O memory
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iow - Write I/O memory
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mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
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tell the CPU whether memory is cacheable and if so the cache write
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mode to use. U-Boot sets up some reasonable values but you can
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adjust then with this command.
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Development Flow
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----------------
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These notes are for those who want to port U-Boot to a new x86 platform.
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Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment.
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The Dediprog em100 can be used on Linux. The em100 tool is available here:
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http://review.coreboot.org/p/em100.git
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On Minnowboard Max the following command line can be used:
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sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r
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A suitable clip for connecting over the SPI flash chip is here:
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http://www.dediprog.com/pd/programmer-accessories/EM-TC-8
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This allows you to override the SPI flash contents for development purposes.
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Typically you can write to the em100 in around 1200ms, considerably faster
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than programming the real flash device each time. The only important
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limitation of the em100 is that it only supports SPI bus speeds up to 20MHz.
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This means that images must be set to boot with that speed. This is an
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Intel-specific feature - e.g. tools/ifttool has an option to set the SPI
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speed in the SPI descriptor region.
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If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly
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easy to fit it in. You can follow the Minnowboard Max implementation, for
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example. Hopefully you will just need to create new files similar to those
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in arch/x86/cpu/baytrail which provide Bay Trail support.
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If you are not using an FSP you have more freedom and more responsibility.
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The ivybridge support works this way, although it still uses a ROM for
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graphics and still has binary blobs containing Intel code. You should aim to
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support all important peripherals on your platform including video and storage.
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Use the device tree for configuration where possible.
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For the microcode you can create a suitable device tree file using the
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microcode tool:
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./tools/microcode-tool -d microcode.dat create <model>
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or if you only have header files and not the full Intel microcode.dat database:
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./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
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-H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \
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create all
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These are written to arch/x86/dts/microcode/ by default.
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Note that it is possible to just add the micrcode for your CPU if you know its
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model. U-Boot prints this information when it starts
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CPU: x86_64, vendor Intel, device 30673h
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so here we can use the M0130673322 file.
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If you platform can display POST codes on two little 7-segment displays on
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the board, then you can use post_code() calls from C or assembler to monitor
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boot progress. This can be good for debugging.
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If not, you can try to get serial working as early as possible. The early
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debug serial port may be useful here. See setup_early_uart() for an example.
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TODO List
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---------
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- Audio
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- Chrome OS verified boot
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- SMI and ACPI support, to provide platform info and facilities to Linux
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References
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----------
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[1] http://www.coreboot.org
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[2] http://www.coreboot.org/~stepan/pci8086,0166.rom
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[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
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[4] http://www.intel.com/fsp
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[5] http://en.wikipedia.org/wiki/Microcode
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