144 lines
2.7 KiB
C
144 lines
2.7 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* CPU specific code
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <asm/arch/ixp425.h>
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#include <asm/system.h>
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ulong loops_per_jiffy;
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static void cache_flush(void);
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo (void)
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{
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unsigned long id;
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int speed = 0;
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asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));
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puts("CPU: Intel IXP425 at ");
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switch ((id & 0x000003f0) >> 4) {
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case 0x1c:
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loops_per_jiffy = 887467;
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speed = 533;
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break;
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case 0x1d:
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loops_per_jiffy = 666016;
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speed = 400;
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break;
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case 0x1f:
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loops_per_jiffy = 442901;
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speed = 266;
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break;
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}
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if (speed)
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printf("%d MHz\n", speed);
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else
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puts("unknown revision\n");
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return 0;
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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int cleanup_before_linux (void)
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{
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/*
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* this function is called just before we call linux
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* it prepares the processor for linux
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*
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* just disable everything that can disturb booting linux
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*/
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disable_interrupts ();
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/* turn off I-cache */
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icache_disable();
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dcache_disable();
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/* flush I-cache */
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cache_flush();
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return 0;
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}
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/* flush I/D-cache */
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static void cache_flush (void)
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{
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unsigned long i = 0;
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asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
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}
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/* FIXME */
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/*
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void pci_init(void)
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{
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return;
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}
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*/
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#ifdef CONFIG_BOOTCOUNT_LIMIT
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void bootcount_store (ulong a)
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{
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volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR);
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save_addr[0] = a;
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save_addr[1] = BOOTCOUNT_MAGIC;
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}
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ulong bootcount_load (void)
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{
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volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR);
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if (save_addr[1] != BOOTCOUNT_MAGIC)
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return 0;
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else
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return save_addr[0];
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}
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#endif /* CONFIG_BOOTCOUNT_LIMIT */
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int cpu_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_IXP4XX_NPE
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npe_initialize(bis);
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#endif
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return 0;
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}
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