213 lines
5.8 KiB
C
213 lines
5.8 KiB
C
/*
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* MPC85xx Internal Memory Map
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*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __FSL_FMAN_H__
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#define __FSL_FMAN_H__
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#include <asm/types.h>
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typedef struct fm_bmi_common {
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u32 fmbm_init; /* BMI initialization */
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u32 fmbm_cfg1; /* BMI configuration1 */
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u32 fmbm_cfg2; /* BMI configuration2 */
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u32 res0[0x5];
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u32 fmbm_ievr; /* interrupt event register */
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u32 fmbm_ier; /* interrupt enable register */
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u32 fmbm_ifr; /* interrupt force register */
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u32 res1[0x5];
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u32 fmbm_arb[0x8]; /* BMI arbitration */
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u32 res2[0x28];
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u32 fmbm_gde; /* global debug enable */
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u32 fmbm_pp[0x3f]; /* BMI port parameters */
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u32 res3;
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u32 fmbm_pfs[0x3f]; /* BMI port FIFO size */
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u32 res4;
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u32 fmbm_ppid[0x3f];/* port partition ID */
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} fm_bmi_common_t;
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typedef struct fm_qmi_common {
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u32 fmqm_gc; /* general configuration register */
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u32 res0;
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u32 fmqm_eie; /* error interrupt event register */
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u32 fmqm_eien; /* error interrupt enable register */
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u32 fmqm_eif; /* error interrupt force register */
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u32 fmqm_ie; /* interrupt event register */
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u32 fmqm_ien; /* interrupt enable register */
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u32 fmqm_if; /* interrupt force register */
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u32 fmqm_gs; /* global status register */
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u32 fmqm_ts; /* task status register */
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u32 fmqm_etfc; /* enqueue total frame counter */
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u32 fmqm_dtfc; /* dequeue total frame counter */
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u32 fmqm_dc0; /* dequeue counter 0 */
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u32 fmqm_dc1; /* dequeue counter 1 */
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u32 fmqm_dc2; /* dequeue counter 2 */
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u32 fmqm_dc3; /* dequeue counter 3 */
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u32 fmqm_dfnoc; /* dequeue FQID not override counter */
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u32 fmqm_dfcc; /* dequeue FQID from context counter */
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u32 fmqm_dffc; /* dequeue FQID from FD counter */
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u32 fmqm_dcc; /* dequeue confirm counter */
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u32 res1[0xc];
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u32 fmqm_dtrc; /* debug trap configuration register */
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u32 fmqm_efddd; /* enqueue frame descriptor dynamic debug */
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u32 res3[0x2];
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u32 res4[0xdc]; /* missing debug regs */
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} fm_qmi_common_t;
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typedef struct fm_bmi {
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u8 res[1024];
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} fm_bmi_t;
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typedef struct fm_qmi {
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u8 res[1024];
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} fm_qmi_t;
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typedef struct fm_parser {
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u8 res[1024];
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} fm_parser_t;
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typedef struct fm_policer {
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u8 res[4*1024];
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} fm_policer_t;
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typedef struct fm_keygen {
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u8 res[4*1024];
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} fm_keygen_t;
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typedef struct fm_dma {
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u32 fmdmsr; /* status register */
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u32 fmdmmr; /* mode register */
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u32 fmdmtr; /* bus threshold register */
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u32 fmdmhy; /* bus hysteresis register */
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u32 fmdmsetr; /* SOS emergency threshold register */
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u32 fmdmtah; /* transfer bus address high register */
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u32 fmdmtal; /* transfer bus address low register */
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u32 fmdmtcid; /* transfer bus communication ID register */
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u32 fmdmra; /* DMA bus internal ram address register */
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u32 fmdmrd; /* DMA bus internal ram data register */
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u32 res0[0xb];
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u32 fmdmdcr; /* debug counter */
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u32 fmdmemsr; /* emrgency smoother register */
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u32 res1;
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u32 fmdmplr[32]; /* FM DMA PID-LIODN # register */
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u32 res[0x3c8];
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} fm_dma_t;
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typedef struct fm_fpm {
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u32 fpmtnc; /* TNUM control */
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u32 fpmprc; /* Port_ID control */
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u32 res0;
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u32 fpmflc; /* flush control */
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u32 fpmdis1; /* dispatch thresholds1 */
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u32 fpmdis2; /* dispatch thresholds2 */
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u32 fmepi; /* error pending interrupts */
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u32 fmrie; /* rams interrupt enable */
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u32 fpmfcevent[0x4];/* FMan controller event 0-3 */
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u32 res1[0x4];
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u32 fpmfcmask[0x4]; /* FMan controller mask 0-3 */
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u32 res2[0x4];
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u32 fpmtsc1; /* timestamp control1 */
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u32 fpmtsc2; /* timestamp control2 */
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u32 fpmtsp; /* time stamp */
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u32 fpmtsf; /* time stamp fraction */
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u32 fpmrcr; /* rams control and event */
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u32 res3[0x3];
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u32 fpmdrd[0x4]; /* data_ram data 0-3 */
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u32 res4[0xc];
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u32 fpmdra; /* data ram access */
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u32 fm_ip_rev_1; /* IP block revision 1 */
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u32 fm_ip_rev_2; /* IP block revision 2 */
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u32 fmrstc; /* reset command */
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u32 fmcld; /* classifier debug control */
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u32 fmnpi; /* normal pending interrupts */
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u32 res5;
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u32 fmnee; /* event and enable */
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u32 fpmcev[0x4]; /* CPU event 0-3 */
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u32 res6[0x4];
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u32 fmfp_ps[0x40]; /* port status */
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u32 res7[0x260];
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u32 fpmts[0x80]; /* task status */
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u32 res8[0xa0];
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} fm_fpm_t;
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typedef struct fm_imem {
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u8 res[4*1024];
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} fm_imem_t;
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typedef struct fm_soft_parser {
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u8 res[4*1024];
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} fm_soft_parser_t;
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typedef struct fm_dtesc {
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u8 res[4*1024];
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} fm_dtsec_t;
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typedef struct fm_mdio {
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u8 res[4*1024];
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} fm_mdio_t;
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typedef struct fm_10gec {
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u8 res[4*1024];
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} fm_10gec_t;
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typedef struct fm_10gec_mdio {
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u8 res[4*1024];
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} fm_10gec_mdio_t;
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typedef struct fm_1588 {
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u8 res[4*1024];
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} fm_1588_t;
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typedef struct ccsr_fman {
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u8 muram[0x80000];
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fm_bmi_common_t fm_bmi_common;
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fm_qmi_common_t fm_qmi_common;
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u8 res0[2048];
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struct {
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fm_bmi_t fm_bmi;
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fm_qmi_t fm_qmi;
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fm_parser_t fm_parser;
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u8 res[1024];
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} port[63];
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fm_policer_t fm_policer;
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fm_keygen_t fm_keygen;
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fm_dma_t fm_dma;
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fm_fpm_t fm_fpm;
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fm_imem_t fm_imem;
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u8 res1[8*1024];
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fm_soft_parser_t fm_soft_parser;
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u8 res2[96*1024];
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struct {
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fm_dtsec_t fm_dtesc;
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fm_mdio_t fm_mdio;
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} mac[4];
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u8 res3[32*1024];
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fm_10gec_t fm_10gec;
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fm_10gec_mdio_t fm_10gec_mdio;
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u8 res4[48*1024];
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fm_1588_t fm_1588;
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u8 res5[4*1024];
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} ccsr_fman_t;
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#endif /*__FSL_FMAN_H__*/
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