130 lines
3.5 KiB
C
130 lines
3.5 KiB
C
/*
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* (C) Copyright 2011 Alex Dubov <oakad@yahoo.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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/*
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* Initialize Local Bus
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*/
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void local_bus_init(void)
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{
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fsl_lbc_t *lbc = LBC_BASE_ADDR;
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out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
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out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
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}
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int checkboard(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
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puts("Board: Mercury Computer Systems, Inc. MPQ-101 ");
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#ifdef CONFIG_PHYS_64BIT
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puts("(36-bit addrmap) ");
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#endif
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putc('\n');
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/*
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* Initialize local bus.
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*/
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local_bus_init();
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/*
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* Hack TSEC 3 and 4 IO voltages.
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*/
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out_be32(&gur->tsec34ioovcr, 0xe7e0); /* 1110 0111 1110 0xxx */
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out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
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out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
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return 0;
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}
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phys_size_t fixed_sdram(void)
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{
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ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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const char *p_mode = getenv("perf_mode");
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puts("Initializing....");
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out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
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out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
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out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
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out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
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if (p_mode && !strcmp("performance", p_mode)) {
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out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_PERF);
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out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_PERF);
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out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_PERF);
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out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_PERF);
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out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_PERF);
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} else {
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out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
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out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
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out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
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out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
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out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
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}
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out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
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out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
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asm("sync;isync");
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udelay(500);
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
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asm("sync; isync");
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udelay(500);
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return ((phys_size_t)1) << CONFIG_SYS_SDRAM_SIZE_LOG;
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}
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void pci_init_board(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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/* PCI is disabled */
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out_be32(&gur->devdisr, in_be32(&gur->devdisr)
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| MPC85xx_DEVDISR_PCI1
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| MPC85xx_DEVDISR_PCI2
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| MPC85xx_DEVDISR_PCIE);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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}
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#endif
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