194 lines
5.4 KiB
C
194 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2017 Microsemi Corporation.
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* Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
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*/
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#ifndef RISCV_CSR_ENCODING_H
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#define RISCV_CSR_ENCODING_H
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#define MSTATUS_UIE 0x00000001
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#define MSTATUS_SIE 0x00000002
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#define MSTATUS_HIE 0x00000004
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#define MSTATUS_MIE 0x00000008
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#define MSTATUS_UPIE 0x00000010
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#define MSTATUS_SPIE 0x00000020
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#define MSTATUS_HPIE 0x00000040
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#define MSTATUS_MPIE 0x00000080
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#define MSTATUS_SPP 0x00000100
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#define MSTATUS_HPP 0x00000600
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#define MSTATUS_MPP 0x00001800
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#define MSTATUS_FS 0x00006000
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#define MSTATUS_XS 0x00018000
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#define MSTATUS_MPRV 0x00020000
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#define MSTATUS_PUM 0x00040000
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#define MSTATUS_VM 0x1F000000
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#define MSTATUS32_SD 0x80000000
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#define MSTATUS64_SD 0x8000000000000000
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#define MCAUSE32_CAUSE 0x7FFFFFFF
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#define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF
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#define MCAUSE32_INT 0x80000000
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#define MCAUSE64_INT 0x8000000000000000
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#define SSTATUS_UIE 0x00000001
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#define SSTATUS_SIE 0x00000002
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#define SSTATUS_UPIE 0x00000010
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#define SSTATUS_SPIE 0x00000020
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#define SSTATUS_SPP 0x00000100
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#define SSTATUS_FS 0x00006000
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#define SSTATUS_XS 0x00018000
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#define SSTATUS_PUM 0x00040000
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#define SSTATUS32_SD 0x80000000
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#define SSTATUS64_SD 0x8000000000000000
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#define MIP_SSIP BIT(IRQ_S_SOFT)
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#define MIP_HSIP BIT(IRQ_H_SOFT)
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#define MIP_MSIP BIT(IRQ_M_SOFT)
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#define MIP_STIP BIT(IRQ_S_TIMER)
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#define MIP_HTIP BIT(IRQ_H_TIMER)
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#define MIP_MTIP BIT(IRQ_M_TIMER)
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#define MIP_SEIP BIT(IRQ_S_EXT)
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#define MIP_HEIP BIT(IRQ_H_EXT)
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#define MIP_MEIP BIT(IRQ_M_EXT)
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#define SIP_SSIP MIP_SSIP
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#define SIP_STIP MIP_STIP
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#define PRV_U 0
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#define PRV_S 1
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#define PRV_H 2
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#define PRV_M 3
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#define VM_MBARE 0
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#define VM_MBB 1
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#define VM_MBBID 2
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#define VM_SV32 8
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#define VM_SV39 9
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#define VM_SV48 10
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#define IRQ_S_SOFT 1
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#define IRQ_H_SOFT 2
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#define IRQ_M_SOFT 3
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#define IRQ_S_TIMER 5
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#define IRQ_H_TIMER 6
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#define IRQ_M_TIMER 7
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#define IRQ_S_EXT 9
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#define IRQ_H_EXT 10
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#define IRQ_M_EXT 11
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#define IRQ_COP 12
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#define IRQ_HOST 13
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#define DEFAULT_RSTVEC 0x00001000
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#define DEFAULT_NMIVEC 0x00001004
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#define DEFAULT_MTVEC 0x00001010
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#define CONFIG_STRING_ADDR 0x0000100C
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#define EXT_IO_BASE 0x40000000
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#define DRAM_BASE 0x80000000
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// page table entry (PTE) fields
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#define PTE_V 0x001 // Valid
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#define PTE_TYPE 0x01E // Type
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#define PTE_R 0x020 // Referenced
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#define PTE_D 0x040 // Dirty
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#define PTE_SOFT 0x380 // Reserved for Software
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#define PTE_TYPE_TABLE 0x00
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#define PTE_TYPE_TABLE_GLOBAL 0x02
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#define PTE_TYPE_URX_SR 0x04
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#define PTE_TYPE_URWX_SRW 0x06
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#define PTE_TYPE_UR_SR 0x08
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#define PTE_TYPE_URW_SRW 0x0A
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#define PTE_TYPE_URX_SRX 0x0C
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#define PTE_TYPE_URWX_SRWX0x0E
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#define PTE_TYPE_SR 0x10
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#define PTE_TYPE_SRW 0x12
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#define PTE_TYPE_SRX 0x14
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#define PTE_TYPE_SRWX 0x16
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#define PTE_TYPE_SR_GLOBAL 0x18
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#define PTE_TYPE_SRW_GLOBAL 0x1A
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#define PTE_TYPE_SRX_GLOBAL 0x1C
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#define PTE_TYPE_SRWX_GLOBAL 0x1E
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#define PTE_PPN_SHIFT 10
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#define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1)
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#define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
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#define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1)
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#define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
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#define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
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#define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1)
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#define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
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#define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \
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typeof(_PTE) (PTE) = (_PTE); \
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typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \
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((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
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(FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
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((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
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#ifdef __riscv
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#ifdef CONFIG_64BIT
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# define MSTATUS_SD MSTATUS64_SD
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# define SSTATUS_SD SSTATUS64_SD
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# define MCAUSE_INT MCAUSE64_INT
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# define MCAUSE_CAUSE MCAUSE64_CAUSE
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# define RISCV_PGLEVEL_BITS 9
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#else
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# define MSTATUS_SD MSTATUS32_SD
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# define SSTATUS_SD SSTATUS32_SD
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# define RISCV_PGLEVEL_BITS 10
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# define MCAUSE_INT MCAUSE32_INT
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# define MCAUSE_CAUSE MCAUSE32_CAUSE
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#endif
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#define RISCV_PGSHIFT 12
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#define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
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#ifndef __ASSEMBLER__
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#ifdef __GNUC__
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#define read_csr(reg) ({ unsigned long __tmp; \
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asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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__tmp; })
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#define write_csr(reg, _val) ({ \
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typeof(_val) (val) = (_val); \
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if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
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else \
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asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
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#define swap_csr(reg, _val) ({ unsigned long __tmp; \
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typeof(_val) (val) = (_val); \
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if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
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else \
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asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
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__tmp; })
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#define set_csr(reg, _bit) ({ unsigned long __tmp; \
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typeof(_bit) (bit) = (_bit); \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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else \
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asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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__tmp; })
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#define clear_csr(reg, _bit) ({ unsigned long __tmp; \
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typeof(_bit) (bit) = (_bit); \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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else \
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asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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__tmp; })
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#define rdtime() read_csr(time)
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#define rdcycle() read_csr(cycle)
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#define rdinstret() read_csr(instret)
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#endif
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#endif
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#endif
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#endif
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