132 lines
2.8 KiB
C
132 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010, 2011
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef _SDRAM_PARAM_H_
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#define _SDRAM_PARAM_H_
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/*
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* Defines the number of 32-bit words provided in each set of SDRAM parameters
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* for arbitration configuration data.
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*/
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#define BCT_SDRAM_ARB_CONFIG_WORDS 27
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enum memory_type {
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MEMORY_TYPE_NONE = 0,
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MEMORY_TYPE_DDR,
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MEMORY_TYPE_LPDDR,
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MEMORY_TYPE_DDR2,
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MEMORY_TYPE_LPDDR2,
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MEMORY_TYPE_NUM,
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MEMORY_TYPE_FORCE32 = 0x7FFFFFFF
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};
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/* Defines the SDRAM parameter structure */
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struct sdram_params {
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enum memory_type memory_type;
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u32 pllm_charge_pump_setup_control;
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u32 pllm_loop_filter_setup_control;
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u32 pllm_input_divider;
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u32 pllm_feedback_divider;
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u32 pllm_post_divider;
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u32 pllm_stable_time;
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u32 emc_clock_divider;
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u32 emc_auto_cal_interval;
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u32 emc_auto_cal_config;
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u32 emc_auto_cal_wait;
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u32 emc_pin_program_wait;
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u32 emc_rc;
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u32 emc_rfc;
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u32 emc_ras;
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u32 emc_rp;
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u32 emc_r2w;
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u32 emc_w2r;
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u32 emc_r2p;
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u32 emc_w2p;
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u32 emc_rd_rcd;
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u32 emc_wr_rcd;
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u32 emc_rrd;
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u32 emc_rext;
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u32 emc_wdv;
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u32 emc_quse;
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u32 emc_qrst;
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u32 emc_qsafe;
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u32 emc_rdv;
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u32 emc_refresh;
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u32 emc_burst_refresh_num;
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u32 emc_pdex2wr;
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u32 emc_pdex2rd;
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u32 emc_pchg2pden;
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u32 emc_act2pden;
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u32 emc_ar2pden;
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u32 emc_rw2pden;
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u32 emc_txsr;
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u32 emc_tcke;
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u32 emc_tfaw;
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u32 emc_trpab;
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u32 emc_tclkstable;
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u32 emc_tclkstop;
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u32 emc_trefbw;
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u32 emc_quseextra;
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u32 emc_fbioc_fg1;
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u32 emc_fbio_dqsib_dly;
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u32 emc_fbio_dqsib_dly_msb;
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u32 emc_fbio_quse_dly;
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u32 emc_fbio_quse_dly_msb;
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u32 emc_fbio_cfg5;
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u32 emc_fbio_cfg6;
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u32 emc_fbio_spare;
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u32 emc_mrs;
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u32 emc_emrs;
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u32 emc_mrw1;
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u32 emc_mrw2;
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u32 emc_mrw3;
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u32 emc_mrw_reset_command;
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u32 emc_mrw_reset_init_wait;
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u32 emc_adr_cfg;
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u32 emc_adr_cfg1;
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u32 emc_emem_cfg;
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u32 emc_low_latency_config;
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u32 emc_cfg;
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u32 emc_cfg2;
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u32 emc_dbg;
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u32 ahb_arbitration_xbar_ctrl;
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u32 emc_cfg_dig_dll;
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u32 emc_dll_xform_dqs;
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u32 emc_dll_xform_quse;
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u32 warm_boot_wait;
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u32 emc_ctt_term_ctrl;
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u32 emc_odt_write;
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u32 emc_odt_read;
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u32 emc_zcal_ref_cnt;
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u32 emc_zcal_wait_cnt;
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u32 emc_zcal_mrw_cmd;
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u32 emc_mrs_reset_dll;
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u32 emc_mrw_zq_init_dev0;
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u32 emc_mrw_zq_init_dev1;
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u32 emc_mrw_zq_init_wait;
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u32 emc_mrs_reset_dll_wait;
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u32 emc_emrs_emr2;
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u32 emc_emrs_emr3;
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u32 emc_emrs_ddr2_dll_enable;
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u32 emc_mrs_ddr2_dll_reset;
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u32 emc_emrs_ddr2_ocd_calib;
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u32 emc_edr2_wait;
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u32 emc_cfg_clktrim0;
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u32 emc_cfg_clktrim1;
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u32 emc_cfg_clktrim2;
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u32 pmc_ddr_pwr;
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u32 apb_misc_gp_xm2cfga_padctrl;
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u32 apb_misc_gp_xm2cfgc_padctrl;
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u32 apb_misc_gp_xm2cfgc_padctrl2;
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u32 apb_misc_gp_xm2cfgd_padctrl;
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u32 apb_misc_gp_xm2cfgd_padctrl2;
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u32 apb_misc_gp_xm2clkcfg_padctrl;
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u32 apb_misc_gp_xm2comp_padctrl;
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u32 apb_misc_gp_xm2vttgen_padctrl;
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u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS];
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};
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#endif
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