70 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			70 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
| /* SPDX-License-Identifier: GPL-2.0+ */
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| /*
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|  * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260_matrix.h]
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|  *
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|  * Copyright (C) 2007 Atmel Corporation.
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|  *
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|  * Memory Controllers (MATRIX, EBI) - System peripherals registers.
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|  * Based on AT91SAM9260 datasheet revision B.
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|  */
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| 
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| #ifndef AT91SAM9260_MATRIX_H
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| #define AT91SAM9260_MATRIX_H
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| 
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| #ifndef __ASSEMBLY__
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| 
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| /*
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|  * This struct defines access to the matrix' maximum of
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|  * 16 masters and 16 slaves.
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|  * However, on the AT91SAM9260/9G20/9XE there exist only
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|  * 6 Masters and 5 Slaves!
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|  */
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| struct at91_matrix {
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| 	u32	mcfg[16];	/* Master Configuration Registers */
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| 	u32	scfg[16];	/* Slave Configuration Registers */
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| 	u32	pras[16][2];	/* Priority Assignment Slave Registers */
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| 	u32	mrcr;		/* Master Remap Control Register */
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| 	u32	filler[0x06];
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| 	u32	ebicsa;		/* EBI Chip Select Assignment Register */
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| };
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| 
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| #endif /* __ASSEMBLY__ */
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| 
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| #define AT91_MATRIX_ULBT_INFINITE	(0 << 0)
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| #define AT91_MATRIX_ULBT_SINGLE		(1 << 0)
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| #define AT91_MATRIX_ULBT_FOUR		(2 << 0)
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| #define AT91_MATRIX_ULBT_EIGHT		(3 << 0)
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| #define AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
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| 
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| #define AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
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| #define AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
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| #define AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
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| #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT	18
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| #define AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
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| #define AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
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| 
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| #define AT91_MATRIX_M0PR_SHIFT		0
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| #define AT91_MATRIX_M1PR_SHIFT		4
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| #define AT91_MATRIX_M2PR_SHIFT		8
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| #define AT91_MATRIX_M3PR_SHIFT		12
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| #define AT91_MATRIX_M4PR_SHIFT		16
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| #define AT91_MATRIX_M5PR_SHIFT		20
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| 
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| #define AT91_MATRIX_RCB0		(1 << 0)
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| #define AT91_MATRIX_RCB1		(1 << 1)
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| 
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| #define AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
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| #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
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| #define AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
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| #define AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
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| #define AT91_MATRIX_DBPUC		(1 << 8)
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| #define AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
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| #define AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
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| #define AT91_MATRIX_EBI_IOSR_SEL	(1 << 17)
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| 
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| /* Maximum Number of Allowed Cycles for a Burst */
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| #define AT91_MATRIX_SLOT_CYCLE		(0xff << 0)
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| #define AT91_MATRIX_SLOT_CYCLE_(x)	(x << 0)
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| 
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| #endif
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