145 lines
2.9 KiB
C
145 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 DENX Software Engineering
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* Heiko Schocher <hs@denx.de>
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*
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* Based on:
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* Copyright (C) 2013 Atmel Corporation
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* Bo Shen <voice.shen@atmel.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91sam9_matrix.h>
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#include <asm/arch/at91_pit.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_wdt.h>
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#include <asm/arch/clk.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void enable_ext_reset(void)
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{
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struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
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writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr);
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}
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void lowlevel_clock_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) {
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/* Enable Main Oscillator */
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writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor);
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/* Wait until Main Oscillator is stable */
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while (!(readl(&pmc->sr) & AT91_PMC_MOSCS))
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;
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}
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/* After stabilization, switch to Main Oscillator */
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if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) {
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unsigned long tmp;
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tmp = readl(&pmc->mckr);
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tmp &= ~AT91_PMC_CSS;
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tmp |= AT91_PMC_CSS_MAIN;
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writel(tmp, &pmc->mckr);
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
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;
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tmp &= ~AT91_PMC_PRES;
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tmp |= AT91_PMC_PRES_1;
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writel(tmp, &pmc->mckr);
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
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;
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}
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return;
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}
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void __weak matrix_init(void)
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{
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}
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void __weak at91_spl_board_init(void)
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{
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}
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void __weak spl_board_init(void)
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{
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}
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void board_init_f(ulong dummy)
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{
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#if CONFIG_IS_ENABLED(OF_CONTROL)
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int ret;
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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#endif
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lowlevel_clock_init();
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#if !defined(CONFIG_WDT_AT91)
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at91_disable_wdt();
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#endif
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/*
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* At this stage the main oscillator is supposed to be enabled
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* PCK = MCK = MOSC
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*/
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at91_pllicpr_init(0x00);
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/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
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at91_plla_init(CONFIG_SYS_AT91_PLLA);
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/* PCK = PLLA = 2 * MCK */
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at91_mck_init(CONFIG_SYS_MCKR);
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/* Switch MCK on PLLA output */
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at91_mck_init(CONFIG_SYS_MCKR_CSS);
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#if defined(CONFIG_SYS_AT91_PLLB)
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/* Configure PLLB */
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at91_pllb_init(CONFIG_SYS_AT91_PLLB);
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#endif
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/* Enable External Reset */
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enable_ext_reset();
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/* Initialize matrix */
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matrix_init();
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gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK;
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/*
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* init timer long enough for using in spl.
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*/
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timer_init();
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/* enable clocks for all PIOs */
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#if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
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at91_periph_clk_enable(ATMEL_ID_PIOAB);
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at91_periph_clk_enable(ATMEL_ID_PIOCD);
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#else
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at91_periph_clk_enable(ATMEL_ID_PIOA);
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at91_periph_clk_enable(ATMEL_ID_PIOB);
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at91_periph_clk_enable(ATMEL_ID_PIOC);
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#endif
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#if defined(CONFIG_SPL_SERIAL_SUPPORT)
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/* init console */
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at91_seriald_hw_init();
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preloader_console_init();
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#endif
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mem_init();
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at91_spl_board_init();
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}
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