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u-boot/arch/riscv/cpu
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Rick Chen f9281b8905 riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled 
This patch will fix prior_stage_fdt_address write failure problem, when
AE350 boots from flash.

When AE350 boots from flash, prior_stage_fdt_address will be flash
address, we shall avoid it to be written.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
 		2019-05-09 16:46:46 +08:00
..
ax25 riscv: ax25: Andes specific cache shall only support in M-mode 2019-04-08 09:45:08 +08:00
generic riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems 2019-02-27 09:12:33 +08:00
Makefile riscv: Move trap handler codes to mtrap.S 2018-12-18 09:56:27 +08:00
cpu.c riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled 2019-05-09 16:46:46 +08:00
mtrap.S riscv: Return to previous privilege level after trap handling 2018-12-18 09:56:27 +08:00
start.S riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled 2019-05-09 16:46:46 +08:00
u-boot.lds riscv: Make start.S available for all targets 2018-10-03 17:48:14 +08:00