394 lines
		
	
	
		
			11 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			394 lines
		
	
	
		
			11 KiB
		
	
	
	
		
			C
		
	
	
	
| /* SPDX-License-Identifier: GPL-2.0+ */
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| /*
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|  * Copyright (c) 2017 Microsemi Corporation.
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|  * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
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|  */
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| 
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| #ifndef RISCV_CSR_ENCODING_H
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| #define RISCV_CSR_ENCODING_H
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| 
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| #ifdef CONFIG_RISCV_SMODE
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| #define MODE_PREFIX(__suffix)	s##__suffix
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| #else
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| #define MODE_PREFIX(__suffix)	m##__suffix
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| #endif
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| 
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| #define MSTATUS_UIE	0x00000001
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| #define MSTATUS_SIE	0x00000002
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| #define MSTATUS_HIE	0x00000004
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| #define MSTATUS_MIE	0x00000008
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| #define MSTATUS_UPIE	0x00000010
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| #define MSTATUS_SPIE	0x00000020
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| #define MSTATUS_HPIE	0x00000040
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| #define MSTATUS_MPIE	0x00000080
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| #define MSTATUS_SPP	0x00000100
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| #define MSTATUS_HPP	0x00000600
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| #define MSTATUS_MPP	0x00001800
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| #define MSTATUS_FS	0x00006000
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| #define MSTATUS_XS	0x00018000
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| #define MSTATUS_MPRV	0x00020000
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| #define MSTATUS_PUM	0x00040000
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| #define MSTATUS_VM	0x1F000000
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| #define MSTATUS32_SD	0x80000000
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| #define MSTATUS64_SD	0x8000000000000000
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| 
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| #define MCAUSE32_CAUSE	0x7FFFFFFF
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| #define MCAUSE64_CAUSE	0x7FFFFFFFFFFFFFFF
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| #define MCAUSE32_INT	0x80000000
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| #define MCAUSE64_INT	0x8000000000000000
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| 
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| #define SSTATUS_UIE	0x00000001
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| #define SSTATUS_SIE	0x00000002
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| #define SSTATUS_UPIE	0x00000010
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| #define SSTATUS_SPIE	0x00000020
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| #define SSTATUS_SPP	0x00000100
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| #define SSTATUS_FS	0x00006000
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| #define SSTATUS_XS	0x00018000
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| #define SSTATUS_PUM	0x00040000
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| #define SSTATUS32_SD	0x80000000
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| #define SSTATUS64_SD	0x8000000000000000
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| 
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| #define MIP_SSIP	BIT(IRQ_S_SOFT)
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| #define MIP_HSIP	BIT(IRQ_H_SOFT)
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| #define MIP_MSIP	BIT(IRQ_M_SOFT)
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| #define MIP_STIP	BIT(IRQ_S_TIMER)
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| #define MIP_HTIP	BIT(IRQ_H_TIMER)
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| #define MIP_MTIP	BIT(IRQ_M_TIMER)
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| #define MIP_SEIP	BIT(IRQ_S_EXT)
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| #define MIP_HEIP	BIT(IRQ_H_EXT)
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| #define MIP_MEIP	BIT(IRQ_M_EXT)
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| 
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| #define SIP_SSIP	MIP_SSIP
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| #define SIP_STIP	MIP_STIP
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| 
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| #define PRV_U	0
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| #define PRV_S	1
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| #define PRV_H	2
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| #define PRV_M	3
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| 
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| #define VM_MBARE	0
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| #define VM_MBB		1
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| #define VM_MBBID	2
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| #define VM_SV32		8
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| #define VM_SV39		9
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| #define VM_SV48		10
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| 
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| #define IRQ_S_SOFT	1
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| #define IRQ_H_SOFT	2
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| #define IRQ_M_SOFT	3
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| #define IRQ_S_TIMER	5
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| #define IRQ_H_TIMER	6
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| #define IRQ_M_TIMER	7
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| #define IRQ_S_EXT	9
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| #define IRQ_H_EXT	10
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| #define IRQ_M_EXT	11
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| #define IRQ_COP		12
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| #define IRQ_HOST	13
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| 
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| #define CAUSE_MISALIGNED_FETCH		0
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| #define CAUSE_FETCH_ACCESS		1
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| #define CAUSE_ILLEGAL_INSTRUCTION	2
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| #define CAUSE_BREAKPOINT		3
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| #define CAUSE_MISALIGNED_LOAD		4
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| #define CAUSE_LOAD_ACCESS		5
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| #define CAUSE_MISALIGNED_STORE		6
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| #define CAUSE_STORE_ACCESS		7
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| #define CAUSE_USER_ECALL		8
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| #define CAUSE_SUPERVISOR_ECALL		9
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| #define CAUSE_MACHINE_ECALL		11
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| #define CAUSE_FETCH_PAGE_FAULT		12
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| #define CAUSE_LOAD_PAGE_FAULT		13
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| #define CAUSE_STORE_PAGE_FAULT		15
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| 
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| #define DEFAULT_RSTVEC		0x00001000
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| #define DEFAULT_NMIVEC		0x00001004
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| #define DEFAULT_MTVEC		0x00001010
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| #define CONFIG_STRING_ADDR	0x0000100C
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| #define EXT_IO_BASE		0x40000000
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| #define DRAM_BASE		0x80000000
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| 
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| // page table entry (PTE) fields
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| #define PTE_V		0x001 // Valid
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| #define PTE_TYPE	0x01E // Type
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| #define PTE_R		0x020 // Referenced
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| #define PTE_D		0x040 // Dirty
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| #define PTE_SOFT	0x380 // Reserved for Software
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| 
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| #define PTE_TYPE_TABLE		0x00
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| #define PTE_TYPE_TABLE_GLOBAL	0x02
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| #define PTE_TYPE_URX_SR		0x04
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| #define PTE_TYPE_URWX_SRW	0x06
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| #define PTE_TYPE_UR_SR		0x08
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| #define PTE_TYPE_URW_SRW	0x0A
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| #define PTE_TYPE_URX_SRX	0x0C
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| #define PTE_TYPE_URWX_SRWX0x0E
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| #define PTE_TYPE_SR		0x10
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| #define PTE_TYPE_SRW		0x12
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| #define PTE_TYPE_SRX		0x14
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| #define PTE_TYPE_SRWX		0x16
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| #define PTE_TYPE_SR_GLOBAL	0x18
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| #define PTE_TYPE_SRW_GLOBAL	0x1A
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| #define PTE_TYPE_SRX_GLOBAL	0x1C
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| #define PTE_TYPE_SRWX_GLOBAL	0x1E
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| 
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| #define PTE_PPN_SHIFT	10
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| 
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| #define PTE_TABLE(PTE)	((0x0000000AU >> ((PTE) & 0x1F)) & 1)
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| #define PTE_UR(PTE)	((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
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| #define PTE_UW(PTE)	((0x00008880U >> ((PTE) & 0x1F)) & 1)
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| #define PTE_UX(PTE)	((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
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| #define PTE_SR(PTE)	((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
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| #define PTE_SW(PTE)	((0x88888880U >> ((PTE) & 0x1F)) & 1)
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| #define PTE_SX(PTE)	((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
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| 
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| #define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \
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| 	typeof(_PTE) (PTE) = (_PTE); \
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| 	typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \
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| 	((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
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| 	(FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
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| 	((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
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| 
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| #ifdef __riscv
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| 
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| #ifdef CONFIG_64BIT
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| # define MSTATUS_SD MSTATUS64_SD
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| # define SSTATUS_SD SSTATUS64_SD
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| # define MCAUSE_INT MCAUSE64_INT
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| # define MCAUSE_CAUSE MCAUSE64_CAUSE
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| # define RISCV_PGLEVEL_BITS 9
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| #else
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| # define MSTATUS_SD MSTATUS32_SD
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| # define SSTATUS_SD SSTATUS32_SD
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| # define RISCV_PGLEVEL_BITS 10
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| # define MCAUSE_INT MCAUSE32_INT
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| # define MCAUSE_CAUSE MCAUSE32_CAUSE
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| #endif
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| 
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| #define RISCV_PGSHIFT 12
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| #define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
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| 
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| /* CSR numbers */
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| #define CSR_FFLAGS		0x1
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| #define CSR_FRM			0x2
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| #define CSR_FCSR		0x3
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| 
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| #define CSR_SSTATUS		0x100
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| #define CSR_SEDELEG		0x102
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| #define CSR_SIDELEG		0x103
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| #define CSR_SIE			0x104
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| #define CSR_STVEC		0x105
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| #define CSR_SCOUNTEREN		0x106
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| #define CSR_SSCRATCH		0x140
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| #define CSR_SEPC		0x141
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| #define CSR_SCAUSE		0x142
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| #define CSR_STVAL		0x143
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| #define CSR_SIP			0x144
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| #define CSR_SATP		0x180
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| 
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| #define CSR_MSTATUS		0x300
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| #define CSR_MISA		0x301
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| #define CSR_MEDELEG		0x302
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| #define CSR_MIDELEG		0x303
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| #define CSR_MIE			0x304
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| #define CSR_MTVEC		0x305
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| #define CSR_MCOUNTEREN		0x306
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| #define CSR_MHPMEVENT3		0x323
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| #define CSR_MHPMEVENT4		0x324
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| #define CSR_MHPMEVENT5		0x325
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| #define CSR_MHPMEVENT6		0x326
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| #define CSR_MHPMEVENT7		0x327
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| #define CSR_MHPMEVENT8		0x328
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| #define CSR_MHPMEVENT9		0x329
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| #define CSR_MHPMEVENT10		0x32a
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| #define CSR_MHPMEVENT11		0x32b
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| #define CSR_MHPMEVENT12		0x32c
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| #define CSR_MHPMEVENT13		0x32d
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| #define CSR_MHPMEVENT14		0x32e
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| #define CSR_MHPMEVENT15		0x32f
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| #define CSR_MHPMEVENT16		0x330
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| #define CSR_MHPMEVENT17		0x331
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| #define CSR_MHPMEVENT18		0x332
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| #define CSR_MHPMEVENT19		0x333
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| #define CSR_MHPMEVENT20		0x334
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| #define CSR_MHPMEVENT21		0x335
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| #define CSR_MHPMEVENT22		0x336
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| #define CSR_MHPMEVENT23		0x337
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| #define CSR_MHPMEVENT24		0x338
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| #define CSR_MHPMEVENT25		0x339
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| #define CSR_MHPMEVENT26		0x33a
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| #define CSR_MHPMEVENT27		0x33b
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| #define CSR_MHPMEVENT28		0x33c
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| #define CSR_MHPMEVENT29		0x33d
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| #define CSR_MHPMEVENT30		0x33e
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| #define CSR_MHPMEVENT31		0x33f
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| #define CSR_MSCRATCH		0x340
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| #define CSR_MEPC		0x341
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| #define CSR_MCAUSE		0x342
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| #define CSR_MTVAL		0x343
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| #define CSR_MIP			0x344
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| #define CSR_PMPCFG0		0x3a0
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| #define CSR_PMPCFG1		0x3a1
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| #define CSR_PMPCFG2		0x3a2
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| #define CSR_PMPCFG3		0x3a3
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| #define CSR_PMPADDR0		0x3b0
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| #define CSR_PMPADDR1		0x3b1
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| #define CSR_PMPADDR2		0x3b2
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| #define CSR_PMPADDR3		0x3b3
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| #define CSR_PMPADDR4		0x3b4
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| #define CSR_PMPADDR5		0x3b5
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| #define CSR_PMPADDR6		0x3b6
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| #define CSR_PMPADDR7		0x3b7
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| #define CSR_PMPADDR8		0x3b8
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| #define CSR_PMPADDR9		0x3b9
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| #define CSR_PMPADDR10		0x3ba
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| #define CSR_PMPADDR11		0x3bb
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| #define CSR_PMPADDR12		0x3bc
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| #define CSR_PMPADDR13		0x3bd
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| #define CSR_PMPADDR14		0x3be
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| #define CSR_PMPADDR15		0x3bf
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| 
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| #define CSR_TSELECT		0x7a0
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| #define CSR_TDATA1		0x7a1
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| #define CSR_TDATA2		0x7a2
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| #define CSR_TDATA3		0x7a3
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| #define CSR_DCSR		0x7b0
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| #define CSR_DPC			0x7b1
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| #define CSR_DSCRATCH		0x7b2
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| 
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| #define CSR_MCYCLE		0xb00
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| #define CSR_MINSTRET		0xb02
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| #define CSR_MHPMCOUNTER3	0xb03
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| #define CSR_MHPMCOUNTER4	0xb04
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| #define CSR_MHPMCOUNTER5	0xb05
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| #define CSR_MHPMCOUNTER6	0xb06
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| #define CSR_MHPMCOUNTER7	0xb07
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| #define CSR_MHPMCOUNTER8	0xb08
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| #define CSR_MHPMCOUNTER9	0xb09
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| #define CSR_MHPMCOUNTER10	0xb0a
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| #define CSR_MHPMCOUNTER11	0xb0b
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| #define CSR_MHPMCOUNTER12	0xb0c
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| #define CSR_MHPMCOUNTER13	0xb0d
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| #define CSR_MHPMCOUNTER14	0xb0e
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| #define CSR_MHPMCOUNTER15	0xb0f
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| #define CSR_MHPMCOUNTER16	0xb10
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| #define CSR_MHPMCOUNTER17	0xb11
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| #define CSR_MHPMCOUNTER18	0xb12
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| #define CSR_MHPMCOUNTER19	0xb13
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| #define CSR_MHPMCOUNTER20	0xb14
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| #define CSR_MHPMCOUNTER21	0xb15
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| #define CSR_MHPMCOUNTER22	0xb16
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| #define CSR_MHPMCOUNTER23	0xb17
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| #define CSR_MHPMCOUNTER24	0xb18
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| #define CSR_MHPMCOUNTER25	0xb19
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| #define CSR_MHPMCOUNTER26	0xb1a
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| #define CSR_MHPMCOUNTER27	0xb1b
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| #define CSR_MHPMCOUNTER28	0xb1c
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| #define CSR_MHPMCOUNTER29	0xb1d
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| #define CSR_MHPMCOUNTER30	0xb1e
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| #define CSR_MHPMCOUNTER31	0xb1f
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| #define CSR_MCYCLEH		0xb80
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| #define CSR_MINSTRETH		0xb82
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| #define CSR_MHPMCOUNTER3H	0xb83
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| #define CSR_MHPMCOUNTER4H	0xb84
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| #define CSR_MHPMCOUNTER5H	0xb85
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| #define CSR_MHPMCOUNTER6H	0xb86
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| #define CSR_MHPMCOUNTER7H	0xb87
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| #define CSR_MHPMCOUNTER8H	0xb88
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| #define CSR_MHPMCOUNTER9H	0xb89
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| #define CSR_MHPMCOUNTER10H	0xb8a
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| #define CSR_MHPMCOUNTER11H	0xb8b
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| #define CSR_MHPMCOUNTER12H	0xb8c
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| #define CSR_MHPMCOUNTER13H	0xb8d
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| #define CSR_MHPMCOUNTER14H	0xb8e
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| #define CSR_MHPMCOUNTER15H	0xb8f
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| #define CSR_MHPMCOUNTER16H	0xb90
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| #define CSR_MHPMCOUNTER17H	0xb91
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| #define CSR_MHPMCOUNTER18H	0xb92
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| #define CSR_MHPMCOUNTER19H	0xb93
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| #define CSR_MHPMCOUNTER20H	0xb94
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| #define CSR_MHPMCOUNTER21H	0xb95
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| #define CSR_MHPMCOUNTER22H	0xb96
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| #define CSR_MHPMCOUNTER23H	0xb97
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| #define CSR_MHPMCOUNTER24H	0xb98
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| #define CSR_MHPMCOUNTER25H	0xb99
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| #define CSR_MHPMCOUNTER26H	0xb9a
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| #define CSR_MHPMCOUNTER27H	0xb9b
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| #define CSR_MHPMCOUNTER28H	0xb9c
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| #define CSR_MHPMCOUNTER29H	0xb9d
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| #define CSR_MHPMCOUNTER30H	0xb9e
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| #define CSR_MHPMCOUNTER31H	0xb9f
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| 
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| #define CSR_CYCLE		0xc00
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| #define CSR_TIME		0xc01
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| #define CSR_INSTRET		0xc02
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| #define CSR_HPMCOUNTER3		0xc03
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| #define CSR_HPMCOUNTER4		0xc04
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| #define CSR_HPMCOUNTER5		0xc05
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| #define CSR_HPMCOUNTER6		0xc06
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| #define CSR_HPMCOUNTER7		0xc07
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| #define CSR_HPMCOUNTER8		0xc08
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| #define CSR_HPMCOUNTER9		0xc09
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| #define CSR_HPMCOUNTER10	0xc0a
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| #define CSR_HPMCOUNTER11	0xc0b
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| #define CSR_HPMCOUNTER12	0xc0c
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| #define CSR_HPMCOUNTER13	0xc0d
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| #define CSR_HPMCOUNTER14	0xc0e
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| #define CSR_HPMCOUNTER15	0xc0f
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| #define CSR_HPMCOUNTER16	0xc10
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| #define CSR_HPMCOUNTER17	0xc11
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| #define CSR_HPMCOUNTER18	0xc12
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| #define CSR_HPMCOUNTER19	0xc13
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| #define CSR_HPMCOUNTER20	0xc14
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| #define CSR_HPMCOUNTER21	0xc15
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| #define CSR_HPMCOUNTER22	0xc16
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| #define CSR_HPMCOUNTER23	0xc17
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| #define CSR_HPMCOUNTER24	0xc18
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| #define CSR_HPMCOUNTER25	0xc19
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| #define CSR_HPMCOUNTER26	0xc1a
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| #define CSR_HPMCOUNTER27	0xc1b
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| #define CSR_HPMCOUNTER28	0xc1c
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| #define CSR_HPMCOUNTER29	0xc1d
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| #define CSR_HPMCOUNTER30	0xc1e
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| #define CSR_HPMCOUNTER31	0xc1f
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| #define CSR_CYCLEH		0xc80
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| #define CSR_TIMEH		0xc81
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| #define CSR_INSTRETH		0xc82
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| #define CSR_HPMCOUNTER3H	0xc83
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| #define CSR_HPMCOUNTER4H	0xc84
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| #define CSR_HPMCOUNTER5H	0xc85
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| #define CSR_HPMCOUNTER6H	0xc86
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| #define CSR_HPMCOUNTER7H	0xc87
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| #define CSR_HPMCOUNTER8H	0xc88
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| #define CSR_HPMCOUNTER9H	0xc89
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| #define CSR_HPMCOUNTER10H	0xc8a
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| #define CSR_HPMCOUNTER11H	0xc8b
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| #define CSR_HPMCOUNTER12H	0xc8c
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| #define CSR_HPMCOUNTER13H	0xc8d
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| #define CSR_HPMCOUNTER14H	0xc8e
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| #define CSR_HPMCOUNTER15H	0xc8f
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| #define CSR_HPMCOUNTER16H	0xc90
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| #define CSR_HPMCOUNTER17H	0xc91
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| #define CSR_HPMCOUNTER18H	0xc92
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| #define CSR_HPMCOUNTER19H	0xc93
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| #define CSR_HPMCOUNTER20H	0xc94
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| #define CSR_HPMCOUNTER21H	0xc95
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| #define CSR_HPMCOUNTER22H	0xc96
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| #define CSR_HPMCOUNTER23H	0xc97
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| #define CSR_HPMCOUNTER24H	0xc98
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| #define CSR_HPMCOUNTER25H	0xc99
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| #define CSR_HPMCOUNTER26H	0xc9a
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| #define CSR_HPMCOUNTER27H	0xc9b
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| #define CSR_HPMCOUNTER28H	0xc9c
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| #define CSR_HPMCOUNTER29H	0xc9d
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| #define CSR_HPMCOUNTER30H	0xc9e
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| #define CSR_HPMCOUNTER31H	0xc9f
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| 
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| #define CSR_MVENDORID		0xf11
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| #define CSR_MARCHID		0xf12
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| #define CSR_MIMPID		0xf13
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| #define CSR_MHARTID		0xf14
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| 
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| #endif /* __riscv */
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| 
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| #endif /* RISCV_CSR_ENCODING_H */
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