105 lines
2.0 KiB
C
105 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016-17 Microsemi Corporation.
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* Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
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*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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#include <common.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/encoding.h>
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static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
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{
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static const char * const exception_code[] = {
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"Instruction address misaligned",
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"Instruction access fault",
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"Illegal instruction",
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"Breakpoint",
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"Load address misaligned",
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"Load access fault",
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"Store/AMO address misaligned",
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"Store/AMO access fault",
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"Environment call from U-mode",
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"Environment call from S-mode",
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"Reserved",
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"Environment call from M-mode",
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"Instruction page fault",
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"Load page fault",
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"Reserved",
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"Store/AMO page fault",
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};
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if (code < ARRAY_SIZE(exception_code)) {
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printf("exception code: %ld , %s , epc %lx , ra %lx\n",
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code, exception_code[code], epc, regs->ra);
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} else {
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printf("reserved exception code: %ld , epc %lx , ra %lx\n",
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code, epc, regs->ra);
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}
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hang();
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}
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int interrupt_init(void)
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{
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return 0;
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}
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/*
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* enable interrupts
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*/
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void enable_interrupts(void)
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{
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}
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/*
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* disable interrupts
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*/
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int disable_interrupts(void)
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{
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return 0;
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}
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ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs)
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{
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ulong is_irq, irq;
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is_irq = (cause & MCAUSE_INT);
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irq = (cause & ~MCAUSE_INT);
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if (is_irq) {
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switch (irq) {
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case IRQ_M_EXT:
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case IRQ_S_EXT:
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external_interrupt(0); /* handle external interrupt */
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break;
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case IRQ_M_TIMER:
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case IRQ_S_TIMER:
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timer_interrupt(0); /* handle timer interrupt */
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break;
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default:
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_exit_trap(cause, epc, regs);
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break;
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};
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} else {
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_exit_trap(cause, epc, regs);
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}
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return epc;
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}
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/*
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*Entry Point for PLIC Interrupt Handler
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*/
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__attribute__((weak)) void external_interrupt(struct pt_regs *regs)
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{
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}
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__attribute__((weak)) void timer_interrupt(struct pt_regs *regs)
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{
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}
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