69 lines
1.8 KiB
C
69 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/gpio.h>
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* These values and defines are taken from the Marvell U-Boot version
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* "u-boot-2013.01-2016_T1.0.eng_drop_v6"
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*/
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#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
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| BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30)))
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#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0))
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#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
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| BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30))
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#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0
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#define DB_DX_AC3_GPP_POL_LOW 0x0
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#define DB_DX_AC3_GPP_POL_MID 0x0
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int board_early_init_f(void)
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{
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/* Configure MPP */
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writel(0x00142222, MVEBU_MPP_BASE + 0x00);
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writel(0x11122000, MVEBU_MPP_BASE + 0x04);
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writel(0x44444004, MVEBU_MPP_BASE + 0x08);
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writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
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writel(0x00000001, MVEBU_MPP_BASE + 0x10);
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/* Set GPP Out value */
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writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
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writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
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/* Set GPP Polarity */
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writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
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writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
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/* Set GPP Out Enable */
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writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
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writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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puts("Board: " CONFIG_SYS_BOARD "\n");
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return 0;
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}
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#endif
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