197 lines
5.4 KiB
C
197 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2011
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* egnite GmbH <info@egnite.de>
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*
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* (C) Copyright 2010
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* Ole Reinhardt <ole.reinhardt@thermotemp.de>
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*/
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/*
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* Ethernut 5 general board support
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*
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* Ethernut is an open source hardware and software project for
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* embedded Ethernet devices. Hardware layouts and CAD files are
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* freely available under BSD-like license.
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*
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* Ethernut 5 is the first member of the Ethernut board family
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* with U-Boot and Linux support. This implementation is based
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* on the original work done by Ole Reinhardt, but heavily modified
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* to support additional features and the latest board revision 5.0F.
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*
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* Main board components are by default:
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*
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* Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash
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* 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM
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* 512 MBytes Micron MT29F4G08ABADA NAND Flash
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* 4 MBytes Atmel AT45DB321D DataFlash
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* SMSC LAN8710 Ethernet PHY
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* Atmel ATmega168 MCU used for power management
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* Linear Technology LTC4411 PoE controller
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*
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* U-Boot relevant board interfaces are:
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*
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* 100 Mbit Ethernet with IEEE 802.3af PoE
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* RS-232 serial port
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* USB host and device
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* MMC/SD-Card slot
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* Expansion port with I2C, SPI and more...
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*
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* Typically the U-Boot image is loaded from serial DataFlash into
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* SDRAM by the samboot boot loader, which is located in internal
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* NOR Flash and provides all essential initializations like CPU
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* and peripheral clocks and, of course, the SDRAM configuration.
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*
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* For testing purposes it is also possibly to directly transfer
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* the image into SDRAM via JTAG. A tested configuration exists
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* for the Turtelizer 2 hardware dongle and the OpenOCD software.
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* In this case the latter will do the basic hardware configuration
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* via its reset-init script.
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*
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* For additional information visit the project home page at
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* http://www.ethernut.de/
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*/
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#include <common.h>
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#include <net.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <atmel_mci.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/arch/at91sam9260_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include "ethernut5_pwrman.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* This is called last during early initialization. Most of the basic
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* hardware interfaces are up and running.
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*
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* The SDRAM hardware has been configured by the first stage boot loader.
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* We only need to announce its size, using u-boot's memory check.
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*/
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int dram_init(void)
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{
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gd->ram_size = get_ram_size(
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(void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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#ifdef CONFIG_CMD_NAND
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static void ethernut5_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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unsigned long csa;
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/* Assign CS3 to NAND/SmartMedia Interface */
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
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writel(csa, &matrix->ebicsa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_DBW_8 |
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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#ifdef CONFIG_SYS_NAND_READY_PIN
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/* Ready pin is optional. */
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at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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#endif
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gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif
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/*
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* This is called first during late initialization.
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*/
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int board_init(void)
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{
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at91_periph_clk_enable(ATMEL_ID_PIOA);
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at91_periph_clk_enable(ATMEL_ID_PIOB);
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at91_periph_clk_enable(ATMEL_ID_PIOC);
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/* Set adress of boot parameters. */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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/* Initialize UARTs and power management. */
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ethernut5_power_init();
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#ifdef CONFIG_CMD_NAND
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ethernut5_nand_hw_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_MACB
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/*
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* This is optionally called last during late initialization.
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*/
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int board_eth_init(bd_t *bis)
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{
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const char *devname;
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unsigned short mode;
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at91_periph_clk_enable(ATMEL_ID_EMAC0);
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/* Need to reset PHY via power management. */
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ethernut5_phy_reset();
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/* Set peripheral pins. */
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at91_macb_hw_init();
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/* Basic EMAC initialization. */
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if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID))
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return -1;
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/*
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* Early board revisions have a pull-down at the PHY's MODE0
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* strap pin, which forces the PHY into power down. Here we
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* switch to all-capable mode.
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*/
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devname = miiphy_get_current_dev();
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if (miiphy_read(devname, 0, 18, &mode) == 0) {
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/* Set mode[2:0] to 0b111. */
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mode |= 0x00E0;
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miiphy_write(devname, 0, 18, mode);
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/* Soft reset overrides strap pins. */
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miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
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}
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/* Sync environment with network devices, needed for nfsroot. */
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return eth_init();
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}
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#endif
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#ifdef CONFIG_GENERIC_ATMEL_MCI
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int board_mmc_init(bd_t *bd)
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{
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at91_periph_clk_enable(ATMEL_ID_MCI);
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/* Initialize MCI hardware. */
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at91_mci_hw_init();
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/* Register the device. */
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return atmel_mci_init((void *)ATMEL_BASE_MCI);
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN);
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}
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#endif
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