137 lines
4.1 KiB
C
137 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2015, Freescale Semiconductor, Inc.
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*/
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/siul.h>
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#include <asm/arch/lpddr2.h>
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#include <asm/arch/mmdc.h>
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volatile int mscr_offset_ck0;
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void lpddr2_config_iomux(uint8_t module)
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{
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int i;
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switch (module) {
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case DDR0:
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mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0);
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writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0));
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writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0));
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writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1));
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writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0));
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writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1));
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for (i = _DDR0_DM0; i <= _DDR0_DM3; i++)
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writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
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for (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++)
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writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
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for (i = _DDR0_A0; i <= _DDR0_A9; i++)
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writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
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for (i = _DDR0_D0; i <= _DDR0_D31; i++)
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writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
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break;
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case DDR1:
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writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0));
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writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0));
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writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1));
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writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0));
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writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1));
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for (i = _DDR1_DM0; i <= _DDR1_DM3; i++)
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writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
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for (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++)
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writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
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for (i = _DDR1_A0; i <= _DDR1_A9; i++)
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writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
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for (i = _DDR1_D0; i <= _DDR1_D31; i++)
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writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
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break;
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}
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}
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void config_mmdc(uint8_t module)
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{
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unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR;
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writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR);
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writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0);
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writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1);
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writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2);
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writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP);
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writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC);
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writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC);
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writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR);
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writel(_MDCTL, mmdc_addr + MMDC_MDCTL);
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writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0);
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while (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) {
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}
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writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR);
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/* Perform ZQ calibration */
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writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL);
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writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL);
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while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) {
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}
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/* Enable MMDC with CS0 */
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writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL);
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/* Complete the initialization sequence as defined by JEDEC */
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writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR);
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writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR);
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writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR);
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writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR);
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/* Set the amount of DRAM */
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/* Set DQS settings based on board type */
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switch (module) {
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case MMDC0:
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writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP);
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writel(MMDC_MPRDDLCTL_MODULE0_VALUE,
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mmdc_addr + MMDC_MPRDDLCTL);
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writel(MMDC_MPWRDLCTL_MODULE0_VALUE,
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mmdc_addr + MMDC_MPWRDLCTL);
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writel(MMDC_MPDGCTRL0_MODULE0_VALUE,
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mmdc_addr + MMDC_MPDGCTRL0);
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writel(MMDC_MPDGCTRL1_MODULE0_VALUE,
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mmdc_addr + MMDC_MPDGCTRL1);
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break;
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case MMDC1:
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writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP);
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writel(MMDC_MPRDDLCTL_MODULE1_VALUE,
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mmdc_addr + MMDC_MPRDDLCTL);
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writel(MMDC_MPWRDLCTL_MODULE1_VALUE,
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mmdc_addr + MMDC_MPWRDLCTL);
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writel(MMDC_MPDGCTRL0_MODULE1_VALUE,
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mmdc_addr + MMDC_MPDGCTRL0);
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writel(MMDC_MPDGCTRL1_MODULE1_VALUE,
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mmdc_addr + MMDC_MPDGCTRL1);
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break;
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}
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writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD);
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writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC);
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writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF);
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writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL);
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writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR);
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}
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