56 lines
1.7 KiB
Plaintext
56 lines
1.7 KiB
Plaintext
/*
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* Copyright (C) 2016, Imagination Technologies Ltd.
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*
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* Zubair Lutfullah Kakakhel, Zubair.Kakakhel@imgtec.com
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*/
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MIPSfpga
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=======================================
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MIPSfpga is an FPGA based development platform by Imagination Technologies
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As we are dealing with a MIPS core instantiated on an FPGA, specifications
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are fluid and can be varied in RTL.
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The example project provided by IMGTEC runs on the Nexys4DDR board by
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Digilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about
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the example project and the Nexys4DDR board:
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- microAptiv UP core m14Kc
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- 50MHz clock speed
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- 128Mbyte DDR RAM at 0x0000_0000
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- 8Kbyte RAM at 0x1000_0000
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- axi_intc at 0x1020_0000
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- axi_uart16550 at 0x1040_0000
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- axi_gpio at 0x1060_0000
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- axi_i2c at 0x10A0_0000
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- custom_gpio at 0x10C0_0000
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- axi_ethernetlite at 0x10E0_0000
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- 8Kbyte BootRAM at 0x1FC0_0000
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- 16Mbyte QPI at 0x1D00_0000
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Boot protocol:
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--------------
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The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
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This is for easy reprogrammibility via JTAG.
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DDR initialization is already handled by a HW IP block.
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When the example project bitstream is loaded, the cpu_reset button
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needs to be pressed.
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The bootram initializes the cache and axi_uart
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Then checks if there is anything non 0xffff_ffff at location 0x1D40_0000
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If there is, then that is considered as u-boot. u-boot is copied from
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0x1D40_0000 to memory and the bootram jumps into u-boot code.
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At this point, the board is ready to load the Linux kernel + buildroot initramfs
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This can be done in multiple ways:
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1- JTAG load the binary and jump into it.
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2- Load kernel stored in the QSPI flash at 0x1D80_0000
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3- Load uImage via tftp. Ethernet works in u-boot.
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e.g. env set server ip 192.168.154.45; dhcp uImage; bootm
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