60 lines
1.8 KiB
Plaintext
60 lines
1.8 KiB
Plaintext
STMicroelectronics Flexible Memory Controller 2 (FMC2)
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NAND Interface
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Required properties:
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- compatible: Should be one of:
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* st,stm32mp15-fmc2
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- reg: NAND flash controller memory areas.
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First region contains the register location.
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Regions 2 to 4 respectively contain the data, command,
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and address space for CS0.
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Regions 5 to 7 contain the same areas for CS1.
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- interrupts: The interrupt number
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- pinctrl-0: Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt)
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- clocks: The clock needed by the NAND flash controller
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Optional properties:
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- resets: Reference to a reset controller asserting the FMC controller
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- dmas: DMA specifiers (see: dma/stm32-mdma.txt)
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- dma-names: Must be "tx", "rx" and "ecc"
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Optional children nodes:
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Children nodes represent the available NAND chips.
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Optional properties:
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- nand-on-flash-bbt: see nand.txt
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- nand-ecc-strength: see nand.txt
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- nand-ecc-step-size: see nand.txt
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The following ECC strength and step size are currently supported:
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- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming)
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- nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
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- nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) (default)
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Example:
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fmc: nand-controller@58002000 {
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compatible = "st,stm32mp15-fmc2";
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reg = <0x58002000 0x1000>,
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<0x80000000 0x1000>,
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<0x88010000 0x1000>,
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<0x88020000 0x1000>,
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<0x81000000 0x1000>,
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<0x89010000 0x1000>,
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<0x89020000 0x1000>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc FMC_K>;
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resets = <&rcc FMC_R>;
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pinctrl-names = "default";
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pinctrl-0 = <&fmc_pins_a>;
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#address-cells = <1>;
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#size-cells = <0>;
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nand@0 {
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reg = <0>;
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nand-on-flash-bbt;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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