568 lines
17 KiB
C
568 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/processor.h>
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#include <fsl_immap.h>
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#include <fsl_ddr.h>
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#include <fsl_errata.h>
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#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
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defined(CONFIG_ARM)
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#include <asm/arch/clock.h>
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#endif
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#define CTLR_INTLV_MASK 0x20000000
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#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \
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defined(CONFIG_SYS_FSL_ERRATUM_A009803)
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static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
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{
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int timeout = 1000;
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ddr_out32(ptr, value);
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while (ddr_in32(ptr) & bits) {
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udelay(100);
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timeout--;
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}
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if (timeout <= 0)
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puts("Error: wait for clear timeout.\n");
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}
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#endif
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#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
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#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
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#endif
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/*
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* regs has the to-be-set values for DDR controller registers
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* ctrl_num is the DDR controller number
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* step: 0 goes through the initialization in one pass
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* 1 sets registers and returns before enabling controller
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* 2 resumes from step 1 and continues to initialize
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* Dividing the initialization to two steps to deassert DDR reset signal
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* to comply with JEDEC specs for RDIMMs.
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*/
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void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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unsigned int ctrl_num, int step)
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{
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unsigned int i, bus_width;
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struct ccsr_ddr __iomem *ddr;
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u32 temp32;
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u32 total_gb_size_per_controller;
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int timeout;
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int mod_bnds = 0;
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
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u32 mr6;
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u32 vref_seq1[3] = {0x80, 0x96, 0x16}; /* for range 1 */
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u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */
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u32 *vref_seq = vref_seq1;
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#endif
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#ifdef CONFIG_FSL_DDR_BIST
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u32 mtcr, err_detect, err_sbe;
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u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
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#endif
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#ifdef CONFIG_FSL_DDR_BIST
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char buffer[CONFIG_SYS_CBSIZE];
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#endif
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switch (ctrl_num) {
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case 0:
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ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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break;
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#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
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case 1:
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ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
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break;
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#endif
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#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
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case 2:
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ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
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break;
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#endif
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#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
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case 3:
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ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
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break;
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#endif
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default:
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printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
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return;
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}
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mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK;
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if (step == 2)
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goto step2;
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/* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/
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ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
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if (regs->ddr_eor)
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ddr_out32(&ddr->eor, regs->ddr_eor);
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ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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if (i == 0) {
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if (mod_bnds) {
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debug("modified bnds\n");
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ddr_out32(&ddr->cs0_bnds,
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(regs->cs[i].bnds & 0xfffefffe) >> 1);
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ddr_out32(&ddr->cs0_config,
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(regs->cs[i].config &
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~CTLR_INTLV_MASK));
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} else {
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ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
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ddr_out32(&ddr->cs0_config, regs->cs[i].config);
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}
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ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
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} else if (i == 1) {
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if (mod_bnds) {
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ddr_out32(&ddr->cs1_bnds,
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(regs->cs[i].bnds & 0xfffefffe) >> 1);
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} else {
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ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
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}
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ddr_out32(&ddr->cs1_config, regs->cs[i].config);
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ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
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} else if (i == 2) {
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if (mod_bnds) {
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ddr_out32(&ddr->cs2_bnds,
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(regs->cs[i].bnds & 0xfffefffe) >> 1);
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} else {
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ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
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}
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ddr_out32(&ddr->cs2_config, regs->cs[i].config);
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ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
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} else if (i == 3) {
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if (mod_bnds) {
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ddr_out32(&ddr->cs3_bnds,
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(regs->cs[i].bnds & 0xfffefffe) >> 1);
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} else {
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ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
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}
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ddr_out32(&ddr->cs3_config, regs->cs[i].config);
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ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
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}
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}
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ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
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ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
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ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
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ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
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ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
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ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
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ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
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ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
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ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
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ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
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ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
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ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
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ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
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ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
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ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
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ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
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ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
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ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
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ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
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ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
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ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
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ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
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ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
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ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
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ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
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ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
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ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
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ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
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ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
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ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
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ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
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ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
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ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009663
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ddr_out32(&ddr->sdram_interval,
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regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE);
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#else
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ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
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#endif
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ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
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ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
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#ifndef CONFIG_SYS_FSL_DDR_EMU
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/*
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* Skip these two registers if running on emulator
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* because emulator doesn't have skew between bytes.
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*/
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if (regs->ddr_wrlvl_cntl_2)
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ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
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if (regs->ddr_wrlvl_cntl_3)
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ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
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#endif
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ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
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ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
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ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
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ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
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ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
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ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
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ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
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#ifdef CONFIG_DEEP_SLEEP
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if (is_warm_boot()) {
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ddr_out32(&ddr->sdram_cfg_2,
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regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
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ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
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ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
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/* DRAM VRef will not be trained */
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ddr_out32(&ddr->ddr_cdr2,
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regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
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} else
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#endif
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{
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ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
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ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
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ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
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ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009803
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/* part 1 of 2 */
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if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
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if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
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ddr_out32(&ddr->ddr_sdram_rcw_2,
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regs->ddr_sdram_rcw_2 & ~0xf0);
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}
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ddr_out32(&ddr->err_disable, regs->err_disable |
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DDR_ERR_DISABLE_APED);
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}
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#else
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ddr_out32(&ddr->err_disable, regs->err_disable);
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#endif
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ddr_out32(&ddr->err_int_en, regs->err_int_en);
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for (i = 0; i < 64; i++) {
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if (regs->debug[i]) {
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debug("Write to debug_%d as %08x\n",
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i+1, regs->debug[i]);
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ddr_out32(&ddr->debug[i], regs->debug[i]);
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}
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
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/* Part 1 of 2 */
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if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
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/* Disable DRAM VRef training */
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ddr_out32(&ddr->ddr_cdr2,
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regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
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/* disable transmit bit deskew */
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temp32 = ddr_in32(&ddr->debug[28]);
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temp32 |= DDR_TX_BD_DIS;
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ddr_out32(&ddr->debug[28], temp32);
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ddr_out32(&ddr->debug[25], 0x9000);
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} else if (fsl_ddr_get_version(ctrl_num) == 0x50201) {
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/* Output enable forced off */
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ddr_out32(&ddr->debug[37], 1 << 31);
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/* Enable Vref training */
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ddr_out32(&ddr->ddr_cdr2,
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regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN);
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} else {
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debug("Erratum A008511 doesn't apply.\n");
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}
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \
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defined(CONFIG_SYS_FSL_ERRATUM_A008511)
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/* Disable D_INIT */
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ddr_out32(&ddr->sdram_cfg_2,
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regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009801
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temp32 = ddr_in32(&ddr->debug[25]);
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temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
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temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
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ddr_out32(&ddr->debug[25], temp32);
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010165
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temp32 = get_ddr_freq(ctrl_num) / 1000000;
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if ((temp32 > 1900) && (temp32 < 2300)) {
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temp32 = ddr_in32(&ddr->debug[28]);
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ddr_out32(&ddr->debug[28], temp32 | 0x000a0000);
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}
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#endif
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/*
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* For RDIMMs, JEDEC spec requires clocks to be stable before reset is
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* deasserted. Clocks start when any chip select is enabled and clock
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* control register is set. Because all DDR components are connected to
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* one reset signal, this needs to be done in two steps. Step 1 is to
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* get the clocks started. Step 2 resumes after reset signal is
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* deasserted.
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*/
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if (step == 1) {
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udelay(200);
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return;
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}
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step2:
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/* Set, but do not enable the memory */
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temp32 = regs->ddr_sdram_cfg;
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temp32 &= ~(SDRAM_CFG_MEM_EN);
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ddr_out32(&ddr->sdram_cfg, temp32);
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/*
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* 500 painful micro-seconds must elapse between
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* the DDR clock setup and the DDR config enable.
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* DDR2 need 200 us, and DDR3 need 500 us from spec,
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* we choose the max, that is 500 us for all of case.
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*/
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udelay(500);
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mb();
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isb();
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#ifdef CONFIG_DEEP_SLEEP
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if (is_warm_boot()) {
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/* enter self-refresh */
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temp32 = ddr_in32(&ddr->sdram_cfg_2);
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temp32 |= SDRAM_CFG2_FRC_SR;
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ddr_out32(&ddr->sdram_cfg_2, temp32);
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/* do board specific memory setup */
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board_mem_sleep_setup();
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temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
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} else
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#endif
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temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
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/* Let the controller go */
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ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN);
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mb();
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isb();
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#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
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defined(CONFIG_SYS_FSL_ERRATUM_A009803)
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/* Part 2 of 2 */
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timeout = 40;
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/* Wait for idle. D_INIT needs to be cleared earlier, or timeout */
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while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
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(timeout > 0)) {
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udelay(1000);
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timeout--;
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}
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if (timeout <= 0) {
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printf("Controler %d timeout, debug_2 = %x\n",
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ctrl_num, ddr_in32(&ddr->debug[1]));
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
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/* This erraum only applies to verion 5.2.0 */
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if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
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/* The vref setting sequence is different for range 2 */
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if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
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vref_seq = vref_seq2;
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/* Set VREF */
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
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continue;
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mr6 = (regs->ddr_sdram_mode_10 >> 16) |
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MD_CNTL_MD_EN |
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MD_CNTL_CS_SEL(i) |
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MD_CNTL_MD_SEL(6) |
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0x00200000;
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temp32 = mr6 | vref_seq[0];
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set_wait_for_bits_clear(&ddr->sdram_md_cntl,
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temp32, MD_CNTL_MD_EN);
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udelay(1);
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debug("MR6 = 0x%08x\n", temp32);
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temp32 = mr6 | vref_seq[1];
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set_wait_for_bits_clear(&ddr->sdram_md_cntl,
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temp32, MD_CNTL_MD_EN);
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udelay(1);
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debug("MR6 = 0x%08x\n", temp32);
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temp32 = mr6 | vref_seq[2];
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set_wait_for_bits_clear(&ddr->sdram_md_cntl,
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temp32, MD_CNTL_MD_EN);
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udelay(1);
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debug("MR6 = 0x%08x\n", temp32);
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}
|
|
ddr_out32(&ddr->sdram_md_cntl, 0);
|
|
temp32 = ddr_in32(&ddr->debug[28]);
|
|
temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
|
|
ddr_out32(&ddr->debug[28], temp32);
|
|
ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */
|
|
/* wait for idle */
|
|
timeout = 40;
|
|
while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
|
|
(timeout > 0)) {
|
|
udelay(1000);
|
|
timeout--;
|
|
}
|
|
if (timeout <= 0) {
|
|
printf("Controler %d timeout, debug_2 = %x\n",
|
|
ctrl_num, ddr_in32(&ddr->debug[1]));
|
|
}
|
|
}
|
|
#endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_A009803
|
|
if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
|
|
/* if it's RDIMM */
|
|
if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
|
|
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
|
|
if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
|
|
continue;
|
|
set_wait_for_bits_clear(&ddr->sdram_md_cntl,
|
|
MD_CNTL_MD_EN |
|
|
MD_CNTL_CS_SEL(i) |
|
|
0x070000ed,
|
|
MD_CNTL_MD_EN);
|
|
udelay(1);
|
|
}
|
|
}
|
|
|
|
ddr_out32(&ddr->err_disable,
|
|
regs->err_disable & ~DDR_ERR_DISABLE_APED);
|
|
}
|
|
#endif
|
|
/* Restore D_INIT */
|
|
ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
|
|
#endif
|
|
|
|
total_gb_size_per_controller = 0;
|
|
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
|
|
if (!(regs->cs[i].config & 0x80000000))
|
|
continue;
|
|
total_gb_size_per_controller += 1 << (
|
|
((regs->cs[i].config >> 14) & 0x3) + 2 +
|
|
((regs->cs[i].config >> 8) & 0x7) + 12 +
|
|
((regs->cs[i].config >> 4) & 0x3) + 0 +
|
|
((regs->cs[i].config >> 0) & 0x7) + 8 +
|
|
((regs->ddr_sdram_cfg_3 >> 4) & 0x3) +
|
|
3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
|
|
26); /* minus 26 (count of 64M) */
|
|
}
|
|
/*
|
|
* total memory / bus width = transactions needed
|
|
* transactions needed / data rate = seconds
|
|
* to add plenty of buffer, double the time
|
|
* For example, 2GB on 666MT/s 64-bit bus takes about 402ms
|
|
* Let's wait for 800ms
|
|
*/
|
|
bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
|
|
>> SDRAM_CFG_DBW_SHIFT);
|
|
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
|
|
(get_ddr_freq(ctrl_num) >> 20)) << 2;
|
|
total_gb_size_per_controller >>= 4; /* shift down to gb size */
|
|
debug("total %d GB\n", total_gb_size_per_controller);
|
|
debug("Need to wait up to %d * 10ms\n", timeout);
|
|
|
|
/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
|
|
while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
|
|
(timeout >= 0)) {
|
|
udelay(10000); /* throttle polling rate */
|
|
timeout--;
|
|
}
|
|
|
|
if (timeout <= 0)
|
|
printf("Waiting for D_INIT timeout. Memory may not work.\n");
|
|
|
|
if (mod_bnds) {
|
|
debug("Reset to original bnds\n");
|
|
ddr_out32(&ddr->cs0_bnds, regs->cs[0].bnds);
|
|
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
|
|
ddr_out32(&ddr->cs1_bnds, regs->cs[1].bnds);
|
|
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
|
|
ddr_out32(&ddr->cs2_bnds, regs->cs[2].bnds);
|
|
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
|
|
ddr_out32(&ddr->cs3_bnds, regs->cs[3].bnds);
|
|
#endif
|
|
#endif
|
|
#endif
|
|
ddr_out32(&ddr->cs0_config, regs->cs[0].config);
|
|
}
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_A009663
|
|
ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
|
|
#endif
|
|
|
|
#ifdef CONFIG_DEEP_SLEEP
|
|
if (is_warm_boot()) {
|
|
/* exit self-refresh */
|
|
temp32 = ddr_in32(&ddr->sdram_cfg_2);
|
|
temp32 &= ~SDRAM_CFG2_FRC_SR;
|
|
ddr_out32(&ddr->sdram_cfg_2, temp32);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_DDR_BIST
|
|
#define BIST_PATTERN1 0xFFFFFFFF
|
|
#define BIST_PATTERN2 0x0
|
|
#define BIST_CR 0x80010000
|
|
#define BIST_CR_EN 0x80000000
|
|
#define BIST_CR_STAT 0x00000001
|
|
/* Perform build-in test on memory. Three-way interleaving is not yet
|
|
* supported by this code. */
|
|
if (env_get_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
|
|
puts("Running BIST test. This will take a while...");
|
|
cs0_config = ddr_in32(&ddr->cs0_config);
|
|
cs0_bnds = ddr_in32(&ddr->cs0_bnds);
|
|
cs1_bnds = ddr_in32(&ddr->cs1_bnds);
|
|
cs2_bnds = ddr_in32(&ddr->cs2_bnds);
|
|
cs3_bnds = ddr_in32(&ddr->cs3_bnds);
|
|
if (cs0_config & CTLR_INTLV_MASK) {
|
|
/* set bnds to non-interleaving */
|
|
ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
|
|
ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
|
|
ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
|
|
ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
|
|
}
|
|
ddr_out32(&ddr->mtp1, BIST_PATTERN1);
|
|
ddr_out32(&ddr->mtp2, BIST_PATTERN1);
|
|
ddr_out32(&ddr->mtp3, BIST_PATTERN2);
|
|
ddr_out32(&ddr->mtp4, BIST_PATTERN2);
|
|
ddr_out32(&ddr->mtp5, BIST_PATTERN1);
|
|
ddr_out32(&ddr->mtp6, BIST_PATTERN1);
|
|
ddr_out32(&ddr->mtp7, BIST_PATTERN2);
|
|
ddr_out32(&ddr->mtp8, BIST_PATTERN2);
|
|
ddr_out32(&ddr->mtp9, BIST_PATTERN1);
|
|
ddr_out32(&ddr->mtp10, BIST_PATTERN2);
|
|
mtcr = BIST_CR;
|
|
ddr_out32(&ddr->mtcr, mtcr);
|
|
timeout = 100;
|
|
while (timeout > 0 && (mtcr & BIST_CR_EN)) {
|
|
mdelay(1000);
|
|
timeout--;
|
|
mtcr = ddr_in32(&ddr->mtcr);
|
|
}
|
|
if (timeout <= 0)
|
|
puts("Timeout\n");
|
|
else
|
|
puts("Done\n");
|
|
err_detect = ddr_in32(&ddr->err_detect);
|
|
err_sbe = ddr_in32(&ddr->err_sbe);
|
|
if (mtcr & BIST_CR_STAT) {
|
|
printf("BIST test failed on controller %d.\n",
|
|
ctrl_num);
|
|
}
|
|
if (err_detect || (err_sbe & 0xffff)) {
|
|
printf("ECC error detected on controller %d.\n",
|
|
ctrl_num);
|
|
}
|
|
|
|
if (cs0_config & CTLR_INTLV_MASK) {
|
|
/* restore bnds registers */
|
|
ddr_out32(&ddr->cs0_bnds, cs0_bnds);
|
|
ddr_out32(&ddr->cs1_bnds, cs1_bnds);
|
|
ddr_out32(&ddr->cs2_bnds, cs2_bnds);
|
|
ddr_out32(&ddr->cs3_bnds, cs3_bnds);
|
|
}
|
|
}
|
|
#endif
|
|
}
|