41 lines
1.0 KiB
C
41 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#ifndef _MV_DDR_TRAINING_DB_H
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#define _MV_DDR_TRAINING_DB_H
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#include "mv_ddr_topology.h"
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/* in ns */
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#define TREFI_LOW 7800
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#define TREFI_HIGH 3900
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enum mv_ddr_page_size {
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MV_DDR_PAGE_SIZE_1K = 1,
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MV_DDR_PAGE_SIZE_2K
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};
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struct mv_ddr_page_element {
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/* 8-bit bus width page size */
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enum mv_ddr_page_size page_size_8bit;
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/* 16-bit bus width page size */
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enum mv_ddr_page_size page_size_16bit;
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};
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/* cas latency value per frequency */
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struct mv_ddr_cl_val_per_freq {
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unsigned int cl_val[MV_DDR_FREQ_LAST];
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};
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u32 mv_ddr_rfc_get(u32 mem);
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unsigned int *mv_ddr_freq_tbl_get(void);
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u32 mv_ddr_freq_get(enum mv_ddr_freq freq);
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u32 mv_ddr_page_size_get(enum mv_ddr_dev_width bus_width, enum mv_ddr_die_capacity mem_size);
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unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_ddr_speed_bin_timing element);
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u32 mv_ddr_cl_val_get(u32 index, u32 freq);
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u32 mv_ddr_cwl_val_get(u32 index, u32 freq);
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#endif /* _MV_DDR_TRAINING_DB_H */
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