132 lines
3.3 KiB
C
132 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Atheros PHY drivers
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*
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* Copyright 2011, 2013 Freescale Semiconductor, Inc.
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* author Andy Fleming
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*/
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#include <common.h>
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#include <phy.h>
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#define AR803x_PHY_DEBUG_ADDR_REG 0x1d
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#define AR803x_PHY_DEBUG_DATA_REG 0x1e
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#define AR803x_DEBUG_REG_5 0x5
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#define AR803x_RGMII_TX_CLK_DLY 0x100
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#define AR803x_DEBUG_REG_0 0x0
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#define AR803x_RGMII_RX_CLK_DLY 0x8000
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static int ar8021_config(struct phy_device *phydev)
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{
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phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
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phydev->supported = phydev->drv->features;
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return 0;
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}
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static int ar8031_config(struct phy_device *phydev)
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{
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
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phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
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AR803x_DEBUG_REG_5);
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phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
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AR803x_RGMII_TX_CLK_DLY);
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}
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
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phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
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AR803x_DEBUG_REG_0);
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phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
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AR803x_RGMII_RX_CLK_DLY);
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}
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phydev->supported = phydev->drv->features;
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genphy_config_aneg(phydev);
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genphy_restart_aneg(phydev);
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return 0;
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}
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static int ar8035_config(struct phy_device *phydev)
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{
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int regval;
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100));
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if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
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/* select debug reg 5 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5);
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/* enable tx delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100);
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}
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if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) {
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/* select debug reg 0 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0);
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/* enable rx delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000);
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}
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phydev->supported = phydev->drv->features;
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genphy_config_aneg(phydev);
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genphy_restart_aneg(phydev);
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return 0;
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}
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static struct phy_driver AR8021_driver = {
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.name = "AR8021",
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.uid = 0x4dd040,
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.mask = 0x4ffff0,
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.features = PHY_GBIT_FEATURES,
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.config = ar8021_config,
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.startup = genphy_startup,
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.shutdown = genphy_shutdown,
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};
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static struct phy_driver AR8031_driver = {
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.name = "AR8031/AR8033",
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.uid = 0x4dd074,
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.mask = 0xffffffef,
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.features = PHY_GBIT_FEATURES,
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.config = ar8031_config,
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.startup = genphy_startup,
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.shutdown = genphy_shutdown,
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};
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static struct phy_driver AR8035_driver = {
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.name = "AR8035",
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.uid = 0x4dd072,
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.mask = 0xffffffef,
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.features = PHY_GBIT_FEATURES,
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.config = ar8035_config,
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.startup = genphy_startup,
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.shutdown = genphy_shutdown,
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};
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int phy_atheros_init(void)
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{
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phy_register(&AR8021_driver);
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phy_register(&AR8031_driver);
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phy_register(&AR8035_driver);
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return 0;
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}
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