552 lines
14 KiB
C
552 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Allwinner SUNXI "glue layer"
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*
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* Copyright © 2015 Hans de Goede <hdegoede@redhat.com>
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* Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
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*
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* Based on the sw_usb "Allwinner OTG Dual Role Controller" code.
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* Copyright 2007-2012 (C) Allwinner Technology Co., Ltd.
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* javen <javen@allwinnertech.com>
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*
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* Based on the DA8xx "glue layer" code.
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* Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
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* Copyright (C) 2005-2006 by Texas Instruments
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*
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* This file is part of the Inventra Controller Driver for Linux.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <phy-sun4i-usb.h>
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#include <reset.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm-generic/gpio.h>
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#include <dm/lists.h>
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#include <dm/root.h>
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#include <linux/usb/musb.h>
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#include "linux-compat.h"
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#include "musb_core.h"
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#include "musb_uboot.h"
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/******************************************************************************
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******************************************************************************
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* From the Allwinner driver
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******************************************************************************
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******************************************************************************/
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/******************************************************************************
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* From include/sunxi_usb_bsp.h
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******************************************************************************/
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/* reg offsets */
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#define USBC_REG_o_ISCR 0x0400
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#define USBC_REG_o_PHYCTL 0x0404
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#define USBC_REG_o_PHYBIST 0x0408
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#define USBC_REG_o_PHYTUNE 0x040c
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#define USBC_REG_o_VEND0 0x0043
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/* Interface Status and Control */
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#define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30
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#define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29
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#define USBC_BP_ISCR_EXT_ID_STATUS 28
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#define USBC_BP_ISCR_EXT_DM_STATUS 27
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#define USBC_BP_ISCR_EXT_DP_STATUS 26
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#define USBC_BP_ISCR_MERGED_VBUS_STATUS 25
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#define USBC_BP_ISCR_MERGED_ID_STATUS 24
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#define USBC_BP_ISCR_ID_PULLUP_EN 17
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#define USBC_BP_ISCR_DPDM_PULLUP_EN 16
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#define USBC_BP_ISCR_FORCE_ID 14
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#define USBC_BP_ISCR_FORCE_VBUS_VALID 12
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#define USBC_BP_ISCR_VBUS_VALID_SRC 10
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#define USBC_BP_ISCR_HOSC_EN 7
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#define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6
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#define USBC_BP_ISCR_ID_CHANGE_DETECT 5
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#define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4
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#define USBC_BP_ISCR_IRQ_ENABLE 3
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#define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2
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#define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1
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#define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0
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/******************************************************************************
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* From usbc/usbc.c
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******************************************************************************/
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#define OFF_SUN6I_AHB_RESET0 0x2c0
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struct sunxi_musb_config {
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struct musb_hdrc_config *config;
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};
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struct sunxi_glue {
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struct musb_host_data mdata;
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struct clk clk;
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struct reset_ctl rst;
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struct sunxi_musb_config *cfg;
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struct device dev;
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struct phy phy;
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};
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#define to_sunxi_glue(d) container_of(d, struct sunxi_glue, dev)
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static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val)
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{
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u32 temp = reg_val;
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temp &= ~BIT(USBC_BP_ISCR_VBUS_CHANGE_DETECT);
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temp &= ~BIT(USBC_BP_ISCR_ID_CHANGE_DETECT);
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temp &= ~BIT(USBC_BP_ISCR_DPDM_CHANGE_DETECT);
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return temp;
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}
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static void USBC_EnableIdPullUp(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val |= BIT(USBC_BP_ISCR_ID_PULLUP_EN);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_EnableDpDmPullUp(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val |= BIT(USBC_BP_ISCR_DPDM_PULLUP_EN);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_ForceIdToLow(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
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reg_val |= (0x02 << USBC_BP_ISCR_FORCE_ID);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_ForceIdToHigh(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
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reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_ForceVbusValidToLow(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
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reg_val |= (0x02 << USBC_BP_ISCR_FORCE_VBUS_VALID);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_ForceVbusValidToHigh(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
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reg_val |= (0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_ConfigFIFO_Base(void)
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{
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u32 reg_value;
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/* config usb fifo, 8kb mode */
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reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
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reg_value &= ~(0x03 << 0);
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reg_value |= BIT(0);
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writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
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}
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/******************************************************************************
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* Needed for the DFU polling magic
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******************************************************************************/
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static u8 last_int_usb;
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bool dfu_usb_get_reset(void)
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{
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return !!(last_int_usb & MUSB_INTR_RESET);
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}
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/******************************************************************************
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* MUSB Glue code
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******************************************************************************/
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static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
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{
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struct musb *musb = __hci;
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irqreturn_t retval = IRQ_NONE;
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/* read and flush interrupts */
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musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
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last_int_usb = musb->int_usb;
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if (musb->int_usb)
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musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
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musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
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if (musb->int_tx)
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musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
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musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
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if (musb->int_rx)
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musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
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if (musb->int_usb || musb->int_tx || musb->int_rx)
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retval |= musb_interrupt(musb);
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return retval;
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}
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/* musb_core does not call enable / disable in a balanced manner <sigh> */
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static bool enabled = false;
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static int sunxi_musb_enable(struct musb *musb)
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{
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struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
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int ret;
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pr_debug("%s():\n", __func__);
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musb_ep_select(musb->mregs, 0);
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musb_writeb(musb->mregs, MUSB_FADDR, 0);
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if (enabled)
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return 0;
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/* select PIO mode */
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musb_writeb(musb->mregs, USBC_REG_o_VEND0, 0);
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if (is_host_enabled(musb)) {
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ret = sun4i_usb_phy_vbus_detect(&glue->phy);
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if (ret == 1) {
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printf("A charger is plugged into the OTG: ");
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return -ENODEV;
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}
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ret = sun4i_usb_phy_id_detect(&glue->phy);
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if (ret == 1) {
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printf("No host cable detected: ");
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return -ENODEV;
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}
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ret = generic_phy_power_on(&glue->phy);
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if (ret) {
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pr_err("failed to power on USB PHY\n");
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return ret;
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}
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}
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USBC_ForceVbusValidToHigh(musb->mregs);
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enabled = true;
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return 0;
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}
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static void sunxi_musb_disable(struct musb *musb)
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{
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struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
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int ret;
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pr_debug("%s():\n", __func__);
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if (!enabled)
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return;
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if (is_host_enabled(musb)) {
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ret = generic_phy_power_off(&glue->phy);
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if (ret) {
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pr_err("failed to power off USB PHY\n");
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return;
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}
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}
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USBC_ForceVbusValidToLow(musb->mregs);
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mdelay(200); /* Wait for the current session to timeout */
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enabled = false;
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}
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static int sunxi_musb_init(struct musb *musb)
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{
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struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
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int ret;
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pr_debug("%s():\n", __func__);
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ret = clk_enable(&glue->clk);
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if (ret) {
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dev_err(dev, "failed to enable clock\n");
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return ret;
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}
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if (reset_valid(&glue->rst)) {
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ret = reset_deassert(&glue->rst);
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if (ret) {
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dev_err(dev, "failed to deassert reset\n");
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goto err_clk;
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}
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}
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ret = generic_phy_init(&glue->phy);
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if (ret) {
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dev_err(dev, "failed to init USB PHY\n");
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goto err_rst;
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}
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musb->isr = sunxi_musb_interrupt;
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USBC_ConfigFIFO_Base();
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USBC_EnableDpDmPullUp(musb->mregs);
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USBC_EnableIdPullUp(musb->mregs);
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if (is_host_enabled(musb)) {
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/* Host mode */
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USBC_ForceIdToLow(musb->mregs);
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} else {
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/* Peripheral mode */
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USBC_ForceIdToHigh(musb->mregs);
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}
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USBC_ForceVbusValidToHigh(musb->mregs);
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return 0;
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err_rst:
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if (reset_valid(&glue->rst))
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reset_assert(&glue->rst);
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err_clk:
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clk_disable(&glue->clk);
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return ret;
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}
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static int sunxi_musb_exit(struct musb *musb)
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{
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struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
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int ret = 0;
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if (generic_phy_valid(&glue->phy)) {
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ret = generic_phy_exit(&glue->phy);
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if (ret) {
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dev_err(dev, "failed to power off usb phy\n");
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return ret;
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}
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}
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if (reset_valid(&glue->rst))
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reset_assert(&glue->rst);
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clk_disable(&glue->clk);
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return 0;
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}
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static void sunxi_musb_pre_root_reset_end(struct musb *musb)
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{
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struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
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sun4i_usb_phy_set_squelch_detect(&glue->phy, false);
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}
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static void sunxi_musb_post_root_reset_end(struct musb *musb)
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{
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struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
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sun4i_usb_phy_set_squelch_detect(&glue->phy, true);
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}
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static const struct musb_platform_ops sunxi_musb_ops = {
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.init = sunxi_musb_init,
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.exit = sunxi_musb_exit,
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.enable = sunxi_musb_enable,
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.disable = sunxi_musb_disable,
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.pre_root_reset_end = sunxi_musb_pre_root_reset_end,
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.post_root_reset_end = sunxi_musb_post_root_reset_end,
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};
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/* Allwinner OTG supports up to 5 endpoints */
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#define SUNXI_MUSB_MAX_EP_NUM 6
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#define SUNXI_MUSB_RAM_BITS 11
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static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
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MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
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MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
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MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
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MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
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MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
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};
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/* H3/V3s OTG supports only 4 endpoints */
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#define SUNXI_MUSB_MAX_EP_NUM_H3 5
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static struct musb_fifo_cfg sunxi_musb_mode_cfg_h3[] = {
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MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
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MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
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MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
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MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
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MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
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};
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static struct musb_hdrc_config musb_config = {
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.fifo_cfg = sunxi_musb_mode_cfg,
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.fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
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.multipoint = true,
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.dyn_fifo = true,
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.num_eps = SUNXI_MUSB_MAX_EP_NUM,
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.ram_bits = SUNXI_MUSB_RAM_BITS,
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};
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static struct musb_hdrc_config musb_config_h3 = {
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.fifo_cfg = sunxi_musb_mode_cfg_h3,
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.fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_h3),
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.multipoint = true,
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.dyn_fifo = true,
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.soft_con = true,
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.num_eps = SUNXI_MUSB_MAX_EP_NUM_H3,
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.ram_bits = SUNXI_MUSB_RAM_BITS,
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};
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static int musb_usb_probe(struct udevice *dev)
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{
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struct sunxi_glue *glue = dev_get_priv(dev);
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struct musb_host_data *host = &glue->mdata;
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struct musb_hdrc_platform_data pdata;
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void *base = dev_read_addr_ptr(dev);
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int ret;
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#ifdef CONFIG_USB_MUSB_HOST
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struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
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#endif
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if (!base)
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return -EINVAL;
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glue->cfg = (struct sunxi_musb_config *)dev_get_driver_data(dev);
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if (!glue->cfg)
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return -EINVAL;
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ret = clk_get_by_index(dev, 0, &glue->clk);
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if (ret) {
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dev_err(dev, "failed to get clock\n");
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return ret;
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}
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ret = reset_get_by_index(dev, 0, &glue->rst);
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if (ret && ret != -ENOENT) {
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dev_err(dev, "failed to get reset\n");
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return ret;
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}
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ret = generic_phy_get_by_name(dev, "usb", &glue->phy);
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if (ret) {
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pr_err("failed to get usb PHY\n");
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return ret;
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}
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memset(&pdata, 0, sizeof(pdata));
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pdata.power = 250;
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pdata.platform_ops = &sunxi_musb_ops;
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pdata.config = glue->cfg->config;
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#ifdef CONFIG_USB_MUSB_HOST
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priv->desc_before_addr = true;
|
|
|
|
pdata.mode = MUSB_HOST;
|
|
host->host = musb_init_controller(&pdata, &glue->dev, base);
|
|
if (!host->host)
|
|
return -EIO;
|
|
|
|
ret = musb_lowlevel_init(host);
|
|
if (!ret)
|
|
printf("Allwinner mUSB OTG (Host)\n");
|
|
#else
|
|
pdata.mode = MUSB_PERIPHERAL;
|
|
host->host = musb_register(&pdata, &glue->dev, base);
|
|
if (!host->host)
|
|
return -EIO;
|
|
|
|
printf("Allwinner mUSB OTG (Peripheral)\n");
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int musb_usb_remove(struct udevice *dev)
|
|
{
|
|
struct sunxi_glue *glue = dev_get_priv(dev);
|
|
struct musb_host_data *host = &glue->mdata;
|
|
|
|
musb_stop(host->host);
|
|
free(host->host);
|
|
host->host = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct sunxi_musb_config sun4i_a10_cfg = {
|
|
.config = &musb_config,
|
|
};
|
|
|
|
static const struct sunxi_musb_config sun6i_a31_cfg = {
|
|
.config = &musb_config,
|
|
};
|
|
|
|
static const struct sunxi_musb_config sun8i_h3_cfg = {
|
|
.config = &musb_config_h3,
|
|
};
|
|
|
|
static const struct udevice_id sunxi_musb_ids[] = {
|
|
{ .compatible = "allwinner,sun4i-a10-musb",
|
|
.data = (ulong)&sun4i_a10_cfg },
|
|
{ .compatible = "allwinner,sun6i-a31-musb",
|
|
.data = (ulong)&sun6i_a31_cfg },
|
|
{ .compatible = "allwinner,sun8i-a33-musb",
|
|
.data = (ulong)&sun6i_a31_cfg },
|
|
{ .compatible = "allwinner,sun8i-h3-musb",
|
|
.data = (ulong)&sun8i_h3_cfg },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(usb_musb) = {
|
|
.name = "sunxi-musb",
|
|
#ifdef CONFIG_USB_MUSB_HOST
|
|
.id = UCLASS_USB,
|
|
#else
|
|
.id = UCLASS_USB_GADGET_GENERIC,
|
|
#endif
|
|
.of_match = sunxi_musb_ids,
|
|
.probe = musb_usb_probe,
|
|
.remove = musb_usb_remove,
|
|
#ifdef CONFIG_USB_MUSB_HOST
|
|
.ops = &musb_usb_ops,
|
|
#endif
|
|
.platdata_auto_alloc_size = sizeof(struct usb_platdata),
|
|
.priv_auto_alloc_size = sizeof(struct sunxi_glue),
|
|
};
|