335 lines
9.7 KiB
C
335 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Timing controller driver for Allwinner SoCs.
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*
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* (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
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* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
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* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/lcdc.h>
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#include <asm/io.h>
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static int lcdc_get_clk_delay(const struct display_timing *mode, int tcon)
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{
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int delay;
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delay = mode->vfront_porch.typ + mode->vsync_len.typ +
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mode->vback_porch.typ;
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if (mode->flags & DISPLAY_FLAGS_INTERLACED)
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delay /= 2;
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if (tcon == 1)
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delay -= 2;
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return (delay > 30) ? 30 : delay;
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}
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void lcdc_init(struct sunxi_lcdc_reg * const lcdc)
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{
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/* Init lcdc */
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writel(0, &lcdc->ctrl); /* Disable tcon */
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writel(0, &lcdc->int0); /* Disable all interrupts */
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/* Disable tcon0 dot clock */
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clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
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/* Set all io lines to tristate */
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writel(0xffffffff, &lcdc->tcon0_io_tristate);
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writel(0xffffffff, &lcdc->tcon1_io_tristate);
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}
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void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth)
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{
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setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
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#ifdef CONFIG_VIDEO_LCD_IF_LVDS
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setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);
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setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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udelay(2); /* delay at least 1200 ns */
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setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB);
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udelay(2); /* delay at least 1200 ns */
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setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC);
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if (depth == 18)
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setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7));
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else
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setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf));
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#else
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setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
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udelay(2); /* delay at least 1200 ns */
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setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);
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udelay(1); /* delay at least 120 ns */
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setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);
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setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
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#endif
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#endif
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}
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void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
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const struct display_timing *mode,
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int clk_div, bool for_ext_vga_dac,
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int depth, int dclk_phase)
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{
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int bp, clk_delay, total, val;
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#ifndef CONFIG_SUNXI_DE2
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/* Use tcon0 */
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clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
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SUNXI_LCDC_CTRL_IO_MAP_TCON0);
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#endif
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clk_delay = lcdc_get_clk_delay(mode, 0);
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writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
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SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
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writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
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SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
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writel(SUNXI_LCDC_X(mode->hactive.typ) |
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SUNXI_LCDC_Y(mode->vactive.typ), &lcdc->tcon0_timing_active);
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bp = mode->hsync_len.typ + mode->hback_porch.typ;
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total = mode->hactive.typ + mode->hfront_porch.typ + bp;
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writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
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SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
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bp = mode->vsync_len.typ + mode->vback_porch.typ;
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total = mode->vactive.typ + mode->vfront_porch.typ + bp;
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writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
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SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
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#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_VIDEO_DE2)
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writel(SUNXI_LCDC_X(mode->hsync_len.typ) |
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SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon0_timing_sync);
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writel(0, &lcdc->tcon0_hv_intf);
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writel(0, &lcdc->tcon0_cpu_intf);
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#endif
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#ifdef CONFIG_VIDEO_LCD_IF_LVDS
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val = (depth == 18) ? 1 : 0;
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writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) |
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SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf);
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#endif
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if (depth == 18 || depth == 16) {
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writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
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writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
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writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
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writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
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writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
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writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
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writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
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writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
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writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
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writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
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writel(((depth == 18) ?
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SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
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SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
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&lcdc->tcon0_frm_ctrl);
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}
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val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase);
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if (mode->flags & DISPLAY_FLAGS_HSYNC_LOW)
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val |= SUNXI_LCDC_TCON_HSYNC_MASK;
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if (mode->flags & DISPLAY_FLAGS_VSYNC_LOW)
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val |= SUNXI_LCDC_TCON_VSYNC_MASK;
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#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
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if (for_ext_vga_dac)
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val = 0;
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#endif
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writel(val, &lcdc->tcon0_io_polarity);
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writel(0, &lcdc->tcon0_io_tristate);
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}
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void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
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const struct display_timing *mode,
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bool ext_hvsync, bool is_composite)
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{
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int bp, clk_delay, total, val, yres;
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#ifndef CONFIG_SUNXI_DE2
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/* Use tcon1 */
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clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
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SUNXI_LCDC_CTRL_IO_MAP_TCON1);
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#endif
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clk_delay = lcdc_get_clk_delay(mode, 1);
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writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
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((mode->flags & DISPLAY_FLAGS_INTERLACED) ?
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SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) |
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SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
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yres = mode->vactive.typ;
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if (mode->flags & DISPLAY_FLAGS_INTERLACED)
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yres /= 2;
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writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres),
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&lcdc->tcon1_timing_source);
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writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres),
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&lcdc->tcon1_timing_scale);
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writel(SUNXI_LCDC_X(mode->hactive.typ) | SUNXI_LCDC_Y(yres),
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&lcdc->tcon1_timing_out);
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bp = mode->hsync_len.typ + mode->hback_porch.typ;
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total = mode->hactive.typ + mode->hfront_porch.typ + bp;
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writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
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SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
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bp = mode->vsync_len.typ + mode->vback_porch.typ;
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total = mode->vactive.typ + mode->vfront_porch.typ + bp;
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if (!(mode->flags & DISPLAY_FLAGS_INTERLACED))
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total *= 2;
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writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
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SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
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writel(SUNXI_LCDC_X(mode->hsync_len.typ) |
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SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon1_timing_sync);
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if (ext_hvsync) {
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val = 0;
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if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
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val |= SUNXI_LCDC_TCON_HSYNC_MASK;
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if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
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val |= SUNXI_LCDC_TCON_VSYNC_MASK;
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writel(val, &lcdc->tcon1_io_polarity);
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clrbits_le32(&lcdc->tcon1_io_tristate,
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SUNXI_LCDC_TCON_VSYNC_MASK |
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SUNXI_LCDC_TCON_HSYNC_MASK);
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}
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#ifdef CONFIG_MACH_SUN5I
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if (is_composite)
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clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK,
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SUNXI_LCDC_MUX_CTRL_SRC0(1));
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#endif
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}
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void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
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int *clk_div, int *clk_double, bool is_composite)
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{
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int value, n, m, min_m, max_m, diff, step;
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int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
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int best_double = 0;
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bool use_mipi_pll = false;
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#ifdef CONFIG_SUNXI_DE2
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step = 6000;
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#else
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step = 3000;
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#endif
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if (tcon == 0) {
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#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_SUNXI_DE2)
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min_m = 6;
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max_m = 127;
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#endif
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#ifdef CONFIG_VIDEO_LCD_IF_LVDS
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min_m = 7;
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max_m = 7;
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#endif
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} else {
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min_m = 1;
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max_m = 15;
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}
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/*
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* Find the lowest divider resulting in a matching clock, if there
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* is no match, pick the closest lower clock, as monitors tend to
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* not sync to higher frequencies.
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*/
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for (m = min_m; m <= max_m; m++) {
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#ifndef CONFIG_SUNXI_DE2
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n = (m * dotclock) / step;
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if ((n >= 9) && (n <= 127)) {
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value = (step * n) / m;
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diff = dotclock - value;
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if (diff < best_diff) {
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best_diff = diff;
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best_m = m;
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best_n = n;
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best_double = 0;
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}
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}
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/* These are just duplicates */
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if (!(m & 1))
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continue;
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#endif
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/* No double clock on DE2 */
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n = (m * dotclock) / (step * 2);
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if ((n >= 9) && (n <= 127)) {
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value = (step * 2 * n) / m;
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diff = dotclock - value;
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if (diff < best_diff) {
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best_diff = diff;
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best_m = m;
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best_n = n;
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best_double = 1;
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}
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}
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}
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#ifdef CONFIG_MACH_SUN6I
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/*
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* Use the MIPI pll if we've been unable to find any matching setting
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* for PLL3, this happens with high dotclocks because of min_m = 6.
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*/
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if (tcon == 0 && best_n == 0) {
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use_mipi_pll = true;
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best_m = 6; /* Minimum m for tcon0 */
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}
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if (use_mipi_pll) {
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clock_set_pll3(297000000); /* Fix the video pll at 297 MHz */
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clock_set_mipi_pll(best_m * dotclock * 1000);
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debug("dotclock: %dkHz = %dkHz via mipi pll\n",
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dotclock, clock_get_mipi_pll() / best_m / 1000);
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} else
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#endif
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{
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clock_set_pll3(best_n * step * 1000);
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debug("dotclock: %dkHz = %dkHz: (%d * %dkHz * %d) / %d\n",
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dotclock,
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(best_double + 1) * clock_get_pll3() / best_m / 1000,
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best_double + 1, step, best_n, best_m);
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}
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if (tcon == 0) {
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u32 pll;
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if (use_mipi_pll)
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pll = CCM_LCD_CH0_CTRL_MIPI_PLL;
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else if (best_double)
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pll = CCM_LCD_CH0_CTRL_PLL3_2X;
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else
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pll = CCM_LCD_CH0_CTRL_PLL3;
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#ifndef CONFIG_SUNXI_DE2
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writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST | pll,
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&ccm->lcd0_ch0_clk_cfg);
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#else
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writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST | pll,
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&ccm->lcd0_clk_cfg);
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#endif
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}
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#ifndef CONFIG_SUNXI_DE2
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else {
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writel(CCM_LCD_CH1_CTRL_GATE |
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(best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :
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CCM_LCD_CH1_CTRL_PLL3) |
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CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
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if (is_composite)
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setbits_le32(&ccm->lcd0_ch1_clk_cfg,
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CCM_LCD_CH1_CTRL_HALF_SCLK1);
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}
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#endif
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*clk_div = best_m;
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*clk_double = best_double;
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}
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