54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuration settings for the Renesas GRPEACH board
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*
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* Copyright (C) 2017-2019 Renesas Electronics
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*/
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#ifndef __GRPEACH_H
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#define __GRPEACH_H
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/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
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#define CONFIG_SYS_CLK_FREQ 66666666
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/* Serial Console */
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#define CONFIG_BAUDRATE 115200
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/* Miscellaneous */
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#define CONFIG_SYS_PBSIZE 256
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#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_ARCH_CPU_INIT
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/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
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#define CONFIG_SYS_LOAD_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_OFFSET 0x80000
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/* Malloc */
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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/* Kernel Boot */
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#define CONFIG_BOOTARGS "ignore_loglevel"
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/* Network interface */
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK
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#define CONFIG_SH_ETHER_CACHE_INVALIDATE
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#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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#endif /* __GRPEACH_H */
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