237 lines
6.2 KiB
C
237 lines
6.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuration settings for the TechNexion TAO-3530 SOM
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* equipped on Thunder baseboard.
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*
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* Edward Lin <linuxfae@technexion.com>
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* Tapani Utriainen <linuxfae@technexion.com>
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*
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* Copyright (C) 2013 Stefan Roese <sr@denx.de>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap.h>
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/* Clock Defines */
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (4 << 20)
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
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/*
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* Hardware drivers
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*/
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/*
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* NS16550 Configuration
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*/
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#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
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/*
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* select serial console configuration
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*/
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#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* commands to include */
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#define CONFIG_SYS_I2C
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#define CONFIG_I2C_MULTI_BUS
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/*
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* TWL4030
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*/
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/*
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* Board NAND Info.
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*/
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand at */
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/* CS0 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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/* Environment information */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x82000000\0" \
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"console=ttyO2,115200n8\0" \
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"mpurate=600\0" \
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"dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
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"tv_mode=omapfb.mode=tv:ntsc\0" \
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"video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
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"lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
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"extra_options= \0" \
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"mmcdev=0\0" \
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"mmcroot=/dev/mmcblk0p2 rw\0" \
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"mmcrootfstype=ext3 rootwait\0" \
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"nandroot=ubi0:rootfs ubi.mtd=4\0" \
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"nandrootfstype=ubifs\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"mpurate=${mpurate} " \
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"${video_mode} " \
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"root=${mmcroot} " \
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"rootfstype=${mmcrootfstype} " \
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"${extra_options}\0" \
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"nandargs=setenv bootargs console=${console} " \
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"mpurate=${mpurate} " \
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"${video_mode} " \
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"${network_setting} " \
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"root=${nandroot} " \
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"rootfstype=${nandrootfstype} "\
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"${extra_options}\0" \
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"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source ${loadaddr}\0" \
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"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"bootm ${loadaddr}\0" \
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"nandboot=echo Booting from nand ...; " \
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"run nandargs; " \
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"nand read ${loadaddr} 280000 400000; " \
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"bootm ${loadaddr}\0" \
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#define CONFIG_BOOTCOMMAND \
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"if mmc rescan ${mmcdev}; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loaduimage; then " \
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"run mmcboot; " \
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"else run nandboot; " \
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"fi; " \
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"fi; " \
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"else run nandboot; fi"
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/*
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* Miscellaneous configurable options
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*/
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/* turn on command-line edit/hist/auto */
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#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
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/* defaults */
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#define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */
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#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
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/* load address */
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/*
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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/*
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* Physical Memory Map
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*/
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/*
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* FLASH and environment organization
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*/
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/* **** PISMO SUPPORT *** */
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
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#define CONFIG_SYS_FLASH_BASE NAND_BASE
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/* Monitor at start of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
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#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
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#define CONFIG_ENV_OFFSET 0x260000
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#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
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#define CONFIG_SYS_INIT_RAM_SIZE 0x800
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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/*
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* USB
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*
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* Currently only EHCI is enabled, the MUSB OTG controller
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* is not enabled.
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*/
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/* USB EHCI */
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#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
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/* Defines for SPL */
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_ECC
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/* NAND boot config */
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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/*
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* Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
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* SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
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*/
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#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
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10, 11, 12, 13 }
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
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CONFIG_SPL_TEXT_BASE)
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/*
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* Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
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* older x-loader implementations. And move the BSS area so that it
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* doesn't overlap with TEXT_BASE.
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*/
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#define CONFIG_SPL_BSS_START_ADDR 0x80100000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#endif /* __CONFIG_H */
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