203 lines
5.9 KiB
C
203 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
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*/
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/*
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* This file contains the configuration parameters for the VCT board
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* family:
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*
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* vct_premium
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* vct_premium_small
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* vct_premium_onenand
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* vct_premium_onenand_small
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* vct_platinum
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* vct_platinum_small
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* vct_platinum_onenand
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* vct_platinum_onenand_small
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* vct_platinumavc
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* vct_platinumavc_small
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* vct_platinumavc_onenand
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* vct_platinumavc_onenand_small
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
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#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
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#define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 << 10)
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#define CONFIG_SYS_MALLOC_LEN (1 << 20)
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#define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10)
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#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
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#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
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#define CONFIG_VCT_NOR
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#endif
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/*
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* UART
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*/
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#ifdef CONFIG_VCT_PLATINUMAVC
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#define UART_1_BASE 0xBDC30000
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#else
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#define UART_1_BASE 0xBF89C000
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#endif
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#define CONFIG_SYS_NS16550_COM1 UART_1_BASE
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#define CONFIG_SYS_NS16550_CLK 921600
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/*
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* SDRAM
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_MBYTES_SDRAM 128
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#define CONFIG_SYS_MEMTEST_START 0x80200000
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#define CONFIG_SYS_MEMTEST_END 0x80400000
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#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */
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#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
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#define CONFIG_NET_RETRY_COUNT 20
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#endif
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/*
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* Commands
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*/
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#if defined(CONFIG_CMD_USB)
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/*
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* USB/EHCI
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*/
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#define CONFIG_USB_EHCI_VCT /* on VCT platform */
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#define CONFIG_EHCI_MMIO_BIG_ENDIAN
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#define CONFIG_EHCI_DESC_BIG_ENDIAN
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#define CONFIG_EHCI_IS_TDI
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
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#endif /* CONFIG_CMD_USB */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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/*
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* FLASH and environment organization
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*/
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#if defined(CONFIG_VCT_NOR)
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#define CONFIG_FLASH_NOT_MEM_MAPPED
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/*
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* We need special accessor functions for the CFI FLASH driver. This
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* can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
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*/
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#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
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/*
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* For the non-memory-mapped NOR FLASH, we need to define the
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* NOR FLASH area. This can't be detected via the addr2info()
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* function, since we check for flash access in the very early
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* U-Boot code, before the NOR FLASH is detected.
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*/
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#define CONFIG_FLASH_BASE 0xb0000000
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#define CONFIG_FLASH_END 0xbfffffff
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/*
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* CFI driver settings
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*/
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#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
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#define CONFIG_SYS_FLASH_BASE 0xb0000000
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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#endif /* CONFIG_VCT_NOR */
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#if defined(CONFIG_VCT_ONENAND)
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#define CONFIG_USE_ONENAND_BOARD_INIT
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#define CONFIG_SYS_ONENAND_BASE 0x00000000 /* this is not real address */
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#define CONFIG_SYS_FLASH_BASE 0x00000000
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#define CONFIG_ENV_ADDR (128 << 10) /* after compr. U-Boot image */
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#define CONFIG_ENV_SIZE (128 << 10) /* erase size */
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#endif /* CONFIG_VCT_ONENAND */
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/*
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* I2C/EEPROM
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */
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#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7f
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define CONFIG_SYS_GPIO_I2C_SCL 11
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#define CONFIG_SYS_GPIO_I2C_SDA 10
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#ifndef __ASSEMBLY__
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int vct_gpio_dir(int pin, int dir);
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void vct_gpio_set(int pin, int val);
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int vct_gpio_get(int pin);
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#endif
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#define I2C_INIT vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
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#define I2C_ACTIVE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
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#define I2C_TRISTATE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
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#define I2C_READ vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
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#define I2C_SDA(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
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#define I2C_SCL(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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/* CAT24WC32 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
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/* 32 byte page write mode using*/
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/* last 5 bits of the address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CONFIG_BOOTCOMMAND "run test3"
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/*
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* UBI configuration
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*/
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/*
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* We need a small, stripped down image to fit into the first 128k OneNAND
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* erase block (gzipped). This image only needs basic commands for FLASH
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* (NOR/OneNAND) usage and Linux kernel booting.
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*/
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#if defined(CONFIG_VCT_SMALL_IMAGE)
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#undef CONFIG_SYS_I2C_SOFT
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#undef CONFIG_SOURCE
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#undef CONFIG_TIMESTAMP
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#endif /* CONFIG_VCT_SMALL_IMAGE */
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#endif /* __CONFIG_H */
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