149 lines
3.4 KiB
C
149 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#include "ddr3_init.h"
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#include "mv_ddr_common.h"
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static char *ddr_type = "DDR3";
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/*
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* generic_init_controller controls D-unit configuration:
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* '1' - dynamic D-unit configuration,
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*/
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u8 generic_init_controller = 1;
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static int mv_ddr_training_params_set(u8 dev_num);
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/*
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* Name: ddr3_init - Main DDR3 Init function
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* Desc: This routine initialize the DDR3 MC and runs HW training.
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* Args: None.
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* Notes:
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* Returns: None.
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*/
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int ddr3_init(void)
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{
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int status;
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int is_manual_cal_done;
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/* Print mv_ddr version */
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mv_ddr_ver_print();
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mv_ddr_pre_training_fixup();
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/* SoC/Board special initializations */
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mv_ddr_pre_training_soc_config(ddr_type);
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/* Set log level for training library */
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mv_ddr_user_log_level_set(DEBUG_BLOCK_ALL);
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mv_ddr_early_init();
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if (mv_ddr_topology_map_update()) {
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printf("mv_ddr: failed to update topology\n");
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return MV_FAIL;
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}
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if (mv_ddr_early_init2() != MV_OK)
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return MV_FAIL;
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/* Set training algorithm's parameters */
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status = mv_ddr_training_params_set(0);
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if (MV_OK != status)
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return status;
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mv_ddr_mc_config();
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is_manual_cal_done = mv_ddr_manual_cal_do();
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mv_ddr_mc_init();
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if (!is_manual_cal_done) {
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}
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status = ddr3_silicon_post_init();
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if (MV_OK != status) {
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printf("DDR3 Post Init - FAILED 0x%x\n", status);
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return status;
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}
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/* PHY initialization (Training) */
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status = hws_ddr3_tip_run_alg(0, ALGO_TYPE_DYNAMIC);
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if (MV_OK != status) {
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printf("%s Training Sequence - FAILED\n", ddr_type);
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return status;
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}
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/* Post MC/PHY initializations */
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mv_ddr_post_training_soc_config(ddr_type);
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mv_ddr_post_training_fixup();
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if (mv_ddr_is_ecc_ena())
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mv_ddr_mem_scrubbing();
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printf("mv_ddr: completed successfully\n");
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return MV_OK;
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}
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/*
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* Name: mv_ddr_training_params_set
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* Desc:
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* Args:
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* Notes: sets internal training params
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* Returns:
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*/
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static int mv_ddr_training_params_set(u8 dev_num)
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{
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struct tune_train_params params;
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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int status;
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u32 cs_num;
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int ck_delay;
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cs_num = mv_ddr_cs_num_get();
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ck_delay = mv_ddr_ck_delay_get();
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/* NOTE: do not remove any field initilization */
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params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
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params.phy_reg3_val = TUNE_TRAINING_PARAMS_PHYREG3VAL;
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params.g_zpri_data = TUNE_TRAINING_PARAMS_PRI_DATA;
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params.g_znri_data = TUNE_TRAINING_PARAMS_NRI_DATA;
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params.g_zpri_ctrl = TUNE_TRAINING_PARAMS_PRI_CTRL;
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params.g_znri_ctrl = TUNE_TRAINING_PARAMS_NRI_CTRL;
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params.g_znodt_data = TUNE_TRAINING_PARAMS_N_ODT_DATA;
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params.g_zpodt_ctrl = TUNE_TRAINING_PARAMS_P_ODT_CTRL;
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params.g_znodt_ctrl = TUNE_TRAINING_PARAMS_N_ODT_CTRL;
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params.g_zpodt_data = TUNE_TRAINING_PARAMS_P_ODT_DATA;
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params.g_dic = TUNE_TRAINING_PARAMS_DIC;
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params.g_rtt_nom = TUNE_TRAINING_PARAMS_RTT_NOM;
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if (cs_num == 1) {
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params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_1CS;
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params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS;
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} else {
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params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_2CS;
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params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS;
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}
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if (ck_delay > 0)
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params.ck_delay = ck_delay;
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/* Use platform specific override ODT value */
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if (tm->odt_config)
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params.g_odt_config = tm->odt_config;
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status = ddr3_tip_tune_training_params(dev_num, ¶ms);
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if (MV_OK != status) {
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printf("%s Training Sequence - FAILED\n", ddr_type);
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return status;
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}
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return MV_OK;
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}
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