381 lines
7.8 KiB
C
381 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#include <dm.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <misc.h>
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#include <pci.h>
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#include <pci_ids.h>
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#include <phy.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <linux/ctype.h>
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#include <linux/delay.h>
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#define PCI_DEVICE_ID_OCTEONTX_SMI 0xA02B
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DECLARE_GLOBAL_DATA_PTR;
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enum octeontx_smi_mode {
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CLAUSE22 = 0,
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CLAUSE45 = 1,
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};
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enum {
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SMI_OP_C22_WRITE = 0,
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SMI_OP_C22_READ = 1,
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SMI_OP_C45_ADDR = 0,
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SMI_OP_C45_WRITE = 1,
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SMI_OP_C45_PRIA = 2,
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SMI_OP_C45_READ = 3,
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};
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union smi_x_clk {
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u64 u;
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struct smi_x_clk_s {
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int phase:8;
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int sample:4;
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int preamble:1;
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int clk_idle:1;
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int reserved_14_14:1;
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int sample_mode:1;
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int sample_hi:5;
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int reserved_21_23:3;
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int mode:1;
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} s;
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};
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union smi_x_cmd {
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u64 u;
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struct smi_x_cmd_s {
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int reg_adr:5;
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int reserved_5_7:3;
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int phy_adr:5;
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int reserved_13_15:3;
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int phy_op:2;
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} s;
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};
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union smi_x_wr_dat {
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u64 u;
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struct smi_x_wr_dat_s {
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unsigned int dat:16;
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int val:1;
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int pending:1;
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} s;
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};
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union smi_x_rd_dat {
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u64 u;
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struct smi_x_rd_dat_s {
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unsigned int dat:16;
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int val:1;
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int pending:1;
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} s;
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};
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union smi_x_en {
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u64 u;
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struct smi_x_en_s {
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int en:1;
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} s;
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};
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#define SMI_X_RD_DAT 0x10ull
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#define SMI_X_WR_DAT 0x08ull
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#define SMI_X_CMD 0x00ull
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#define SMI_X_CLK 0x18ull
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#define SMI_X_EN 0x20ull
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struct octeontx_smi_priv {
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void __iomem *baseaddr;
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enum octeontx_smi_mode mode;
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};
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#define MDIO_TIMEOUT 10000
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void octeontx_smi_setmode(struct mii_dev *bus, enum octeontx_smi_mode mode)
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{
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struct octeontx_smi_priv *priv = bus->priv;
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union smi_x_clk smix_clk;
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smix_clk.u = readq(priv->baseaddr + SMI_X_CLK);
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smix_clk.s.mode = mode;
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smix_clk.s.preamble = mode == CLAUSE45;
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writeq(smix_clk.u, priv->baseaddr + SMI_X_CLK);
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priv->mode = mode;
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}
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int octeontx_c45_addr(struct mii_dev *bus, int addr, int devad, int regnum)
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{
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struct octeontx_smi_priv *priv = bus->priv;
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union smi_x_cmd smix_cmd;
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union smi_x_wr_dat smix_wr_dat;
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unsigned long timeout = MDIO_TIMEOUT;
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smix_wr_dat.u = 0;
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smix_wr_dat.s.dat = regnum;
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writeq(smix_wr_dat.u, priv->baseaddr + SMI_X_WR_DAT);
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smix_cmd.u = 0;
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smix_cmd.s.phy_op = SMI_OP_C45_ADDR;
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smix_cmd.s.phy_adr = addr;
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smix_cmd.s.reg_adr = devad;
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writeq(smix_cmd.u, priv->baseaddr + SMI_X_CMD);
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do {
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smix_wr_dat.u = readq(priv->baseaddr + SMI_X_WR_DAT);
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udelay(100);
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timeout--;
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} while (smix_wr_dat.s.pending && timeout);
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return timeout == 0;
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}
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int octeontx_phy_read(struct mii_dev *bus, int addr, int devad, int regnum)
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{
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struct octeontx_smi_priv *priv = bus->priv;
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union smi_x_cmd smix_cmd;
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union smi_x_rd_dat smix_rd_dat;
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unsigned long timeout = MDIO_TIMEOUT;
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int ret;
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enum octeontx_smi_mode mode = (devad < 0) ? CLAUSE22 : CLAUSE45;
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debug("RD: Mode: %u, baseaddr: %p, addr: %d, devad: %d, reg: %d\n",
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mode, priv->baseaddr, addr, devad, regnum);
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octeontx_smi_setmode(bus, mode);
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if (mode == CLAUSE45) {
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ret = octeontx_c45_addr(bus, addr, devad, regnum);
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debug("RD: ret: %u\n", ret);
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if (ret)
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return 0;
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}
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smix_cmd.u = 0;
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smix_cmd.s.phy_adr = addr;
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if (mode == CLAUSE45) {
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smix_cmd.s.reg_adr = devad;
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smix_cmd.s.phy_op = SMI_OP_C45_READ;
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} else {
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smix_cmd.s.reg_adr = regnum;
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smix_cmd.s.phy_op = SMI_OP_C22_READ;
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}
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writeq(smix_cmd.u, priv->baseaddr + SMI_X_CMD);
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do {
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smix_rd_dat.u = readq(priv->baseaddr + SMI_X_RD_DAT);
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udelay(10);
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timeout--;
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} while (smix_rd_dat.s.pending && timeout);
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debug("SMIX_RD_DAT: %lx\n", (unsigned long)smix_rd_dat.u);
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return smix_rd_dat.s.dat;
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}
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int octeontx_phy_write(struct mii_dev *bus, int addr, int devad, int regnum,
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u16 value)
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{
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struct octeontx_smi_priv *priv = bus->priv;
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union smi_x_cmd smix_cmd;
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union smi_x_wr_dat smix_wr_dat;
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unsigned long timeout = MDIO_TIMEOUT;
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int ret;
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enum octeontx_smi_mode mode = (devad < 0) ? CLAUSE22 : CLAUSE45;
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debug("WR: Mode: %u, baseaddr: %p, addr: %d, devad: %d, reg: %d\n",
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mode, priv->baseaddr, addr, devad, regnum);
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if (mode == CLAUSE45) {
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ret = octeontx_c45_addr(bus, addr, devad, regnum);
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debug("WR: ret: %u\n", ret);
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if (ret)
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return ret;
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}
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smix_wr_dat.u = 0;
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smix_wr_dat.s.dat = value;
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writeq(smix_wr_dat.u, priv->baseaddr + SMI_X_WR_DAT);
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smix_cmd.u = 0;
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smix_cmd.s.phy_adr = addr;
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if (mode == CLAUSE45) {
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smix_cmd.s.reg_adr = devad;
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smix_cmd.s.phy_op = SMI_OP_C45_WRITE;
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} else {
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smix_cmd.s.reg_adr = regnum;
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smix_cmd.s.phy_op = SMI_OP_C22_WRITE;
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}
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writeq(smix_cmd.u, priv->baseaddr + SMI_X_CMD);
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do {
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smix_wr_dat.u = readq(priv->baseaddr + SMI_X_WR_DAT);
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udelay(10);
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timeout--;
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} while (smix_wr_dat.s.pending && timeout);
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debug("SMIX_WR_DAT: %lx\n", (unsigned long)smix_wr_dat.u);
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return timeout == 0;
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}
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int octeontx_smi_reset(struct mii_dev *bus)
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{
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struct octeontx_smi_priv *priv = bus->priv;
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union smi_x_en smi_en;
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smi_en.s.en = 0;
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writeq(smi_en.u, priv->baseaddr + SMI_X_EN);
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smi_en.s.en = 1;
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writeq(smi_en.u, priv->baseaddr + SMI_X_EN);
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octeontx_smi_setmode(bus, CLAUSE22);
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return 0;
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}
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/* PHY XS initialization, primarily for RXAUI
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*
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*/
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int rxaui_phy_xs_init(struct mii_dev *bus, int phy_addr)
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{
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int reg;
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ulong start_time;
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int phy_id1, phy_id2;
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int oui, model_number;
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phy_id1 = octeontx_phy_read(bus, phy_addr, 1, 0x2);
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phy_id2 = octeontx_phy_read(bus, phy_addr, 1, 0x3);
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model_number = (phy_id2 >> 4) & 0x3F;
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debug("%s model %x\n", __func__, model_number);
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oui = phy_id1;
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oui <<= 6;
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oui |= (phy_id2 >> 10) & 0x3F;
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debug("%s oui %x\n", __func__, oui);
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switch (oui) {
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case 0x5016:
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if (model_number == 9) {
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debug("%s +\n", __func__);
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/* Perform hardware reset in XGXS control */
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reg = octeontx_phy_read(bus, phy_addr, 4, 0x0);
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if ((reg & 0xffff) < 0)
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goto read_error;
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reg |= 0x8000;
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octeontx_phy_write(bus, phy_addr, 4, 0x0, reg);
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start_time = get_timer(0);
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do {
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reg = octeontx_phy_read(bus, phy_addr, 4, 0x0);
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if ((reg & 0xffff) < 0)
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goto read_error;
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} while ((reg & 0x8000) && get_timer(start_time) < 500);
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if (reg & 0x8000) {
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printf("HW reset for M88X3120 PHY failed");
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printf("MII_BMCR: 0x%x\n", reg);
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return -1;
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}
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/* program 4.49155 with 0x5 */
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octeontx_phy_write(bus, phy_addr, 4, 0xc003, 0x5);
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}
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break;
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default:
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break;
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}
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return 0;
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read_error:
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debug("M88X3120 PHY config read failed\n");
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return -1;
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}
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int octeontx_smi_probe(struct udevice *dev)
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{
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pci_dev_t bdf = dm_pci_get_bdf(dev);
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struct octeontx_smi_priv *priv;
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struct mii_dev *bus;
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int ret, cnt = 0;
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ofnode subnode;
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u64 baseaddr;
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debug("SMI PCI device: %x\n", bdf);
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if (!dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM)) {
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printf("Failed to map PCI region for bdf %x\n", bdf);
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return -1;
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}
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dev_for_each_subnode(subnode, dev) {
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if (!ofnode_device_is_compatible(subnode,
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"cavium,thunder-8890-mdio"))
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continue;
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if (ofnode_read_u64(subnode, "reg", &baseaddr))
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continue;
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bus = mdio_alloc();
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priv = malloc(sizeof(*priv));
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if (!bus || !priv) {
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printf("Failed to allocate OcteonTX MDIO bus # %u\n",
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dev_seq(dev));
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return -1;
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}
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bus->read = octeontx_phy_read;
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bus->write = octeontx_phy_write;
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bus->reset = octeontx_smi_reset;
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bus->priv = priv;
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priv->mode = CLAUSE22;
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priv->baseaddr = (void __iomem *)baseaddr;
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debug("mdio base addr %p\n", priv->baseaddr);
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/* use given name or generate its own unique name */
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snprintf(bus->name, MDIO_NAME_LEN, "smi%d", cnt++);
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ret = mdio_register(bus);
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if (ret)
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return ret;
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}
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return 0;
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}
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static const struct udevice_id octeontx_smi_ids[] = {
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{ .compatible = "cavium,thunder-8890-mdio-nexus" },
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{}
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};
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U_BOOT_DRIVER(octeontx_smi) = {
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.name = "octeontx_smi",
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.id = UCLASS_MISC,
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.probe = octeontx_smi_probe,
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.of_match = octeontx_smi_ids,
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};
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static struct pci_device_id octeontx_smi_supported[] = {
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{ PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_SMI) },
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{}
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};
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U_BOOT_PCI_DEVICE(octeontx_smi, octeontx_smi_supported);
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