508 lines
14 KiB
C
508 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* TI PHY drivers
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*
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*/
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#include <common.h>
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#include <phy.h>
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#include <linux/compat.h>
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#include <malloc.h>
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#include <dm.h>
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#include <dt-bindings/net/ti-dp83869.h>
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/* TI DP83869 */
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#define DP83869_DEVADDR 0x1f
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#define MII_DP83869_PHYCTRL 0x10
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#define MII_DP83869_MICR 0x12
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#define MII_DP83869_CFG2 0x14
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#define MII_DP83869_BISCR 0x16
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#define DP83869_CTRL 0x1f
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#define DP83869_CFG4 0x1e
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/* Extended Registers */
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#define DP83869_GEN_CFG3 0x0031
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#define DP83869_RGMIICTL 0x0032
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#define DP83869_STRAP_STS1 0x006E
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#define DP83869_RGMIIDCTL 0x0086
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#define DP83869_IO_MUX_CFG 0x0170
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#define DP83869_OP_MODE 0x01df
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#define DP83869_FX_CTRL 0x0c00
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#define DP83869_SW_RESET BIT(15)
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#define DP83869_SW_RESTART BIT(14)
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/* MICR Interrupt bits */
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#define MII_DP83869_MICR_AN_ERR_INT_EN BIT(15)
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#define MII_DP83869_MICR_SPEED_CHNG_INT_EN BIT(14)
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#define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
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#define MII_DP83869_MICR_PAGE_RXD_INT_EN BIT(12)
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#define MII_DP83869_MICR_AUTONEG_COMP_INT_EN BIT(11)
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#define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN BIT(10)
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#define MII_DP83869_MICR_FALSE_CARRIER_INT_EN BIT(8)
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#define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
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#define MII_DP83869_MICR_WOL_INT_EN BIT(3)
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#define MII_DP83869_MICR_XGMII_ERR_INT_EN BIT(2)
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#define MII_DP83869_MICR_POL_CHNG_INT_EN BIT(1)
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#define MII_DP83869_MICR_JABBER_INT_EN BIT(0)
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#define MII_DP83869_BMCR_DEFAULT (BMCR_ANENABLE | \
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BMCR_FULLDPLX | \
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BMCR_SPEED1000)
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/* This is the same bit mask as the BMCR so re-use the BMCR default */
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#define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT
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/* CFG1 bits */
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#define DP83869_CFG1_DEFAULT (ADVERTISE_1000HALF | \
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ADVERTISE_1000FULL | \
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CTL1000_AS_MASTER)
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/* RGMIICTL bits */
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#define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1)
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#define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0)
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/* STRAP_STS1 bits */
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#define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0)
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#define DP83869_STRAP_STS1_RESERVED BIT(11)
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#define DP83869_STRAP_MIRROR_ENABLED BIT(12)
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/* PHY CTRL bits */
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#define DP83869_PHYCR_RX_FIFO_DEPTH_SHIFT 12
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#define DP83869_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
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#define DP83869_PHYCR_TX_FIFO_DEPTH_SHIFT 14
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#define DP83869_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
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#define DP83869_PHYCR_RESERVED_MASK BIT(11)
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#define DP83869_PHYCR_MDI_CROSSOVER_SHIFT 5
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#define DP83869_PHYCR_MDI_CROSSOVER_MDIX 2
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#define DP83869_PHY_CTRL_DEFAULT 0x48
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/* RGMIIDCTL bits */
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#define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4
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#define DP83869_CLK_DELAY_DEF 7
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/* CFG2 bits */
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#define MII_DP83869_CFG2_SPEEDOPT_10EN 0x0040
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#define MII_DP83869_CFG2_SGMII_AUTONEGEN 0x0080
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#define MII_DP83869_CFG2_SPEEDOPT_ENH 0x0100
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#define MII_DP83869_CFG2_SPEEDOPT_CNT 0x0800
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#define MII_DP83869_CFG2_SPEEDOPT_INTLOW 0x2000
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#define MII_DP83869_CFG2_MASK 0x003F
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/* User setting - can be taken from DTS */
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#define DEFAULT_FIFO_DEPTH DP83869_PHYCR_FIFO_DEPTH_4_B_NIB
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/* IO_MUX_CFG bits */
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#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
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#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
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#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
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#define DP83869_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
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#define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
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#define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK \
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GENMASK(0x1f, DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT)
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/* CFG3 bits */
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#define DP83869_CFG3_PORT_MIRROR_EN BIT(0)
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/* OP MODE bits */
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#define DP83869_OP_MODE_MII BIT(5)
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#define DP83869_SGMII_RGMII_BRIDGE BIT(6)
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enum {
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DP83869_PORT_MIRRORING_KEEP,
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DP83869_PORT_MIRRORING_EN,
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DP83869_PORT_MIRRORING_DIS,
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};
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struct dp83869_private {
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int tx_fifo_depth;
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int rx_fifo_depth;
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s32 rx_int_delay;
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s32 tx_int_delay;
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int io_impedance;
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int port_mirroring;
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bool set_clk_output;
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int clk_output_sel;
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int mode;
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};
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static int dp83869_readext(struct phy_device *phydev, int addr, int devad, int reg)
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{
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return phy_read_mmd(phydev, devad, reg);
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}
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static int dp83869_writeext(struct phy_device *phydev, int addr, int devad, int reg, u16 val)
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{
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return phy_write_mmd(phydev, devad, reg, val);
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}
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static int dp83869_config_port_mirroring(struct phy_device *phydev)
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{
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struct dp83869_private *dp83869 =
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(struct dp83869_private *)phydev->priv;
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u16 val;
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val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_CFG4);
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if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN)
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val |= DP83869_CFG3_PORT_MIRROR_EN;
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else
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val &= ~DP83869_CFG3_PORT_MIRROR_EN;
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phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_CFG4, val);
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return 0;
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}
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#ifdef CONFIG_DM_ETH
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static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500,
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1750, 2000, 2250, 2500, 2750, 3000,
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3250, 3500, 3750, 4000};
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static int dp83869_set_strapped_mode(struct phy_device *phydev)
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{
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struct dp83869_private *dp83869 = phydev->priv;
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int val;
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val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
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if (val < 0)
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return val;
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dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK;
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return 0;
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}
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/**
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* dp83869_data_init - Convenience function for setting PHY specific data
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*
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* @phydev: the phy_device struct
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*/
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static int dp83869_of_init(struct phy_device *phydev)
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{
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struct dp83869_private * const dp83869 = phydev->priv;
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const int delay_entries = ARRAY_SIZE(dp83869_internal_delay);
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int ret;
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ofnode node;
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node = phy_get_ofnode(phydev);
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if (!ofnode_valid(node))
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return -EINVAL;
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dp83869->io_impedance = -EINVAL;
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/* Optional configuration, set to default if required */
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dp83869->clk_output_sel = ofnode_read_u32_default(node, "ti,clk-output-sel",
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DP83869_CLK_O_SEL_CHN_A_RCLK);
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if (dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK &&
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dp83869->clk_output_sel != DP83869_CLK_O_SEL_OFF)
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dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK;
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/* If operation mode is not set use setting from straps */
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ret = ofnode_read_s32(node, "ti,op-mode", &dp83869->mode);
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if (ret == 0) {
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if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
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dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
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return -EINVAL;
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} else {
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ret = dp83869_set_strapped_mode(phydev);
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if (ret)
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return ret;
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}
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if (ofnode_read_bool(node, "ti,max-output-impedance"))
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dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX;
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else if (ofnode_read_bool(node, "ti,min-output-impedance"))
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dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN;
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if (ofnode_read_bool(node, "enet-phy-lane-swap")) {
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dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
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} else {
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ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
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if (ret < 0)
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return ret;
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if (ret & DP83869_STRAP_MIRROR_ENABLED)
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dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
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else
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dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS;
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}
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dp83869->rx_fifo_depth = ofnode_read_s32_default(node, "rx-fifo-depth",
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DP83869_PHYCR_FIFO_DEPTH_4_B_NIB);
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dp83869->tx_fifo_depth = ofnode_read_s32_default(node, "tx-fifo-depth",
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DP83869_PHYCR_FIFO_DEPTH_4_B_NIB);
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/* RX delay *must* be specified if internal delay of RX is used. */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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dp83869->rx_int_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps",
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DP83869_CLK_DELAY_DEF);
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if (dp83869->rx_int_delay > delay_entries) {
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dp83869->rx_int_delay = DP83869_CLK_DELAY_DEF;
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pr_debug("rx-internal-delay-ps not set/invalid, default to %ups\n",
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dp83869_internal_delay[dp83869->rx_int_delay]);
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}
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dp83869->rx_int_delay = dp83869_internal_delay[dp83869->rx_int_delay];
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}
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/* TX delay *must* be specified if internal delay of RX is used. */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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dp83869->tx_int_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps",
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DP83869_CLK_DELAY_DEF);
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if (dp83869->tx_int_delay > delay_entries) {
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dp83869->tx_int_delay = DP83869_CLK_DELAY_DEF;
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pr_debug("tx-internal-delay-ps not set/invalid, default to %ups\n",
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dp83869_internal_delay[dp83869->tx_int_delay]);
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}
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dp83869->tx_int_delay = dp83869_internal_delay[dp83869->tx_int_delay];
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}
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return 0;
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}
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#else
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static int dp83869_of_init(struct phy_device *phydev)
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{
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struct dp83869_private *dp83869 = phydev->priv;
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dp83869->rx_int_delay = DP83869_RGMIIDCTL_2_25_NS;
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dp83869->tx_int_delay = DP83869_RGMIIDCTL_2_75_NS;
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dp83869->fifo_depth = DEFAULT_FIFO_DEPTH;
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dp83869->io_impedance = -EINVAL;
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return 0;
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}
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#endif /* CONFIG_OF_MDIO */
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static int dp83869_configure_rgmii(struct phy_device *phydev,
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struct dp83869_private *dp83869)
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{
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int ret = 0, val;
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if (phy_interface_is_rgmii(phydev)) {
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val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL);
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if (val < 0)
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return val;
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val &= ~(DP83869_PHYCR_TX_FIFO_DEPTH_MASK | DP83869_PHYCR_RX_FIFO_DEPTH_MASK);
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val |= (dp83869->tx_fifo_depth << DP83869_PHYCR_TX_FIFO_DEPTH_SHIFT);
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val |= (dp83869->rx_fifo_depth << DP83869_PHYCR_RX_FIFO_DEPTH_SHIFT);
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ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL, val);
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if (ret)
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return ret;
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}
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if (dp83869->io_impedance >= 0) {
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val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG);
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val &= ~DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
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val |= dp83869->io_impedance & DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
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ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG, val);
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if (ret)
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return ret;
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}
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return ret;
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}
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static int dp83869_configure_mode(struct phy_device *phydev,
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struct dp83869_private *dp83869)
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{
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int phy_ctrl_val;
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int ret, val;
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if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
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dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
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return -EINVAL;
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/* Below init sequence for each operational mode is defined in
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* section 9.4.8 of the datasheet.
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*/
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ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
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dp83869->mode);
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if (ret)
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return ret;
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ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, MII_DP83869_BMCR_DEFAULT);
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if (ret)
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return ret;
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phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_PHYCR_RX_FIFO_DEPTH_SHIFT |
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dp83869->tx_fifo_depth << DP83869_PHYCR_TX_FIFO_DEPTH_SHIFT |
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DP83869_PHY_CTRL_DEFAULT);
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switch (dp83869->mode) {
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case DP83869_RGMII_COPPER_ETHERNET:
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ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL,
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phy_ctrl_val);
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if (ret)
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return ret;
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ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, DP83869_CFG1_DEFAULT);
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if (ret)
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return ret;
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ret = dp83869_configure_rgmii(phydev, dp83869);
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if (ret)
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return ret;
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break;
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case DP83869_RGMII_SGMII_BRIDGE:
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val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE);
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val |= DP83869_SGMII_RGMII_BRIDGE;
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ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, val);
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if (ret)
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return ret;
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ret = phy_write_mmd(phydev, DP83869_DEVADDR,
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DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
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if (ret)
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return ret;
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break;
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case DP83869_1000M_MEDIA_CONVERT:
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ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL,
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phy_ctrl_val);
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if (ret)
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return ret;
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ret = phy_write_mmd(phydev, DP83869_DEVADDR,
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DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
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if (ret)
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return ret;
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break;
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case DP83869_100M_MEDIA_CONVERT:
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ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL,
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phy_ctrl_val);
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if (ret)
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return ret;
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break;
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case DP83869_SGMII_COPPER_ETHERNET:
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ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL,
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phy_ctrl_val);
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if (ret)
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return ret;
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ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, DP83869_CFG1_DEFAULT);
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if (ret)
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return ret;
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ret = phy_write_mmd(phydev, DP83869_DEVADDR,
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DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
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if (ret)
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return ret;
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break;
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default:
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return -EINVAL;
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}
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return ret;
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}
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static int dp83869_config(struct phy_device *phydev)
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{
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struct dp83869_private *dp83869;
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unsigned int val;
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int ret;
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dp83869 = (struct dp83869_private *)phydev->priv;
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ret = dp83869_of_init(phydev);
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if (ret)
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return ret;
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ret = dp83869_configure_mode(phydev, dp83869);
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if (ret)
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return ret;
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if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP)
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dp83869_config_port_mirroring(phydev);
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/* Clock output selection if muxing property is set */
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if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) {
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val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG);
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val &= ~DP83869_IO_MUX_CFG_CLK_O_SEL_MASK;
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val |= dp83869->clk_output_sel << DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT;
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ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG, val);
|
|
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (phy_interface_is_rgmii(phydev)) {
|
|
ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL,
|
|
dp83869->rx_int_delay |
|
|
dp83869->tx_int_delay << DP83869_RGMII_TX_CLK_DELAY_SHIFT);
|
|
if (ret)
|
|
return ret;
|
|
|
|
val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL);
|
|
val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
|
|
DP83869_RGMII_RX_CLK_DELAY_EN);
|
|
|
|
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
|
|
val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN |
|
|
DP83869_RGMII_RX_CLK_DELAY_EN);
|
|
|
|
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
|
|
val &= ~DP83869_RGMII_TX_CLK_DELAY_EN;
|
|
|
|
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
|
|
val &= ~DP83869_RGMII_RX_CLK_DELAY_EN;
|
|
|
|
ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL,
|
|
val);
|
|
}
|
|
|
|
genphy_config_aneg(phydev);
|
|
return 0;
|
|
}
|
|
|
|
static int dp83869_probe(struct phy_device *phydev)
|
|
{
|
|
struct dp83869_private *dp83869;
|
|
|
|
dp83869 = kzalloc(sizeof(*dp83869), GFP_KERNEL);
|
|
if (!dp83869)
|
|
return -ENOMEM;
|
|
|
|
phydev->priv = dp83869;
|
|
return 0;
|
|
}
|
|
|
|
static struct phy_driver DP83869_driver = {
|
|
.name = "TI DP83869",
|
|
.uid = 0x2000a0f1,
|
|
.mask = 0xfffffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.probe = dp83869_probe,
|
|
.config = &dp83869_config,
|
|
.startup = &genphy_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
.readext = dp83869_readext,
|
|
.writeext = dp83869_writeext
|
|
};
|
|
|
|
int phy_dp83869_init(void)
|
|
{
|
|
phy_register(&DP83869_driver);
|
|
return 0;
|
|
}
|