104 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			104 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
/*
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 * Copyright (c) 2016 Google, Inc
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 * Written by Simon Glass <sjg@chromium.org>
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 *
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 * SPDX-License-Identifier:	GPL-2.0+
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 */
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#include <common.h>
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#include <div64.h>
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#include <dm.h>
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#include <pwm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3288.h>
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#include <asm/arch/grf_rk3288.h>
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#include <asm/arch/pwm.h>
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#include <power/regulator.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rk_pwm_priv {
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	struct rk3288_pwm *regs;
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	struct rk3288_grf *grf;
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};
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static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
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			     uint duty_ns)
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{
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	struct rk_pwm_priv *priv = dev_get_priv(dev);
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	struct rk3288_pwm *regs = priv->regs;
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	unsigned long period, duty;
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	debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
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	writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
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		PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE |
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		RK_PWM_DISABLE,
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		®s->ctrl);
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	period = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * period_ns, 1000000);
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	duty = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * duty_ns, 1000000);
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	writel(period, ®s->period_hpr);
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	writel(duty, ®s->duty_lpr);
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	debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
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	return 0;
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}
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static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
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{
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	struct rk_pwm_priv *priv = dev_get_priv(dev);
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	struct rk3288_pwm *regs = priv->regs;
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	debug("%s: Enable '%s'\n", __func__, dev->name);
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	clrsetbits_le32(®s->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0);
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	return 0;
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}
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static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
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{
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	struct rk_pwm_priv *priv = dev_get_priv(dev);
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	struct regmap *map;
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	priv->regs = (struct rk3288_pwm *)dev_get_addr(dev);
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	map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_GRF);
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	if (IS_ERR(map))
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		return PTR_ERR(map);
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	priv->grf = regmap_get_range(map, 0);
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	return 0;
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}
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static int rk_pwm_probe(struct udevice *dev)
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{
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	struct rk_pwm_priv *priv = dev_get_priv(dev);
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	rk_setreg(&priv->grf->soc_con2, 1 << 0);
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	return 0;
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}
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static const struct pwm_ops rk_pwm_ops = {
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	.set_config	= rk_pwm_set_config,
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	.set_enable	= rk_pwm_set_enable,
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};
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static const struct udevice_id rk_pwm_ids[] = {
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	{ .compatible = "rockchip,rk3288-pwm" },
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	{ }
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};
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U_BOOT_DRIVER(rk_pwm) = {
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	.name	= "rk_pwm",
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	.id	= UCLASS_PWM,
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	.of_match = rk_pwm_ids,
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	.ops	= &rk_pwm_ops,
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	.ofdata_to_platdata	= rk_pwm_ofdata_to_platdata,
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	.probe		= rk_pwm_probe,
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	.priv_auto_alloc_size	= sizeof(struct rk_pwm_priv),
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};
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