145 lines
3.3 KiB
C
145 lines
3.3 KiB
C
/*
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* LPC32xx SSP interface (SPI mode)
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*
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* (C) Copyright 2014 DENX Software Engineering GmbH
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* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/compat.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/arch/clk.h>
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/* SSP chip registers */
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struct ssp_regs {
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u32 cr0;
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u32 cr1;
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u32 data;
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u32 sr;
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u32 cpsr;
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u32 imsc;
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u32 ris;
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u32 mis;
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u32 icr;
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u32 dmacr;
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};
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/* CR1 register defines */
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#define SSP_CR1_SSP_ENABLE 0x0002
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/* SR register defines */
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#define SSP_SR_TNF 0x0002
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/* SSP status RX FIFO not empty bit */
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#define SSP_SR_RNE 0x0004
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/* lpc32xx spi slave */
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struct lpc32xx_spi_slave {
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struct spi_slave slave;
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struct ssp_regs *regs;
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};
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static inline struct lpc32xx_spi_slave *to_lpc32xx_spi_slave(
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struct spi_slave *slave)
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{
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return container_of(slave, struct lpc32xx_spi_slave, slave);
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}
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/* spi_init is called during boot when CONFIG_CMD_SPI is defined */
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void spi_init(void)
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{
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/*
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* nothing to do: clocking was enabled in lpc32xx_ssp_enable()
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* and configuration will be done in spi_setup_slave()
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*/
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}
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/* the following is called in sequence by do_spi_xfer() */
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struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
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{
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struct lpc32xx_spi_slave *lslave;
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/* we only set up SSP0 for now, so ignore bus */
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if (mode & SPI_3WIRE) {
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error("3-wire mode not supported");
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return NULL;
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}
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if (mode & SPI_SLAVE) {
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error("slave mode not supported\n");
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return NULL;
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}
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if (mode & SPI_PREAMBLE) {
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error("preamble byte skipping not supported\n");
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return NULL;
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}
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lslave = spi_alloc_slave(struct lpc32xx_spi_slave, bus, cs);
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if (!lslave) {
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printf("SPI_error: Fail to allocate lpc32xx_spi_slave\n");
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return NULL;
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}
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lslave->regs = (struct ssp_regs *)SSP0_BASE;
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/*
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* 8 bit frame, SPI fmt, 500kbps -> clock divider is 26.
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* Set SCR to 0 and CPSDVSR to 26.
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*/
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writel(0x7, &lslave->regs->cr0); /* 8-bit chunks, SPI, 1 clk/bit */
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writel(26, &lslave->regs->cpsr); /* SSP clock = HCLK/26 = 500kbps */
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writel(0, &lslave->regs->imsc); /* do not raise any interrupts */
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writel(0, &lslave->regs->icr); /* clear any pending interrupt */
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writel(0, &lslave->regs->dmacr); /* do not do DMAs */
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writel(SSP_CR1_SSP_ENABLE, &lslave->regs->cr1); /* enable SSP0 */
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return &lslave->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct lpc32xx_spi_slave *lslave = to_lpc32xx_spi_slave(slave);
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debug("(lpc32xx) spi_free_slave: 0x%08x\n", (u32)lslave);
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free(lslave);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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/* only one bus and slave so far, always available */
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return 0;
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct lpc32xx_spi_slave *lslave = to_lpc32xx_spi_slave(slave);
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int bytelen = bitlen >> 3;
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int idx_out = 0;
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int idx_in = 0;
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int start_time;
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start_time = get_timer(0);
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while ((idx_out < bytelen) || (idx_in < bytelen)) {
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int status = readl(&lslave->regs->sr);
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if ((idx_out < bytelen) && (status & SSP_SR_TNF))
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writel(((u8 *)dout)[idx_out++], &lslave->regs->data);
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if ((idx_in < bytelen) && (status & status & SSP_SR_RNE))
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((u8 *)din)[idx_in++] = readl(&lslave->regs->data);
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if (get_timer(start_time) >= CONFIG_LPC32XX_SSP_TIMEOUT)
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return -1;
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}
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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/* do nothing */
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}
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