290 lines
7.8 KiB
C
290 lines
7.8 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "ddr3_init.h"
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static u32 bist_offset = 32;
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enum hws_pattern sweep_pattern = PATTERN_KILLER_DQ0;
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static int ddr3_tip_bist_operation(u32 dev_num,
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enum hws_access_type access_type,
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u32 if_id,
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enum hws_bist_operation oper_type);
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/*
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* BIST activate
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*/
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int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
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enum hws_access_type access_type, u32 if_num,
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enum hws_dir direction,
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enum hws_stress_jump addr_stress_jump,
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enum hws_pattern_duration duration,
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enum hws_bist_operation oper_type,
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u32 offset, u32 cs_num, u32 pattern_addr_length)
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{
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u32 tx_burst_size;
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u32 delay_between_burst;
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u32 rd_mode, val;
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u32 poll_cnt = 0, max_poll = 1000, i, start_if, end_if;
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struct pattern_info *pattern_table = ddr3_tip_get_pattern_table();
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u32 read_data[MAX_INTERFACE_NUM];
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struct hws_topology_map *tm = ddr3_get_topology_map();
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/* ODPG Write enable from BIST */
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CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num,
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ODPG_DATA_CONTROL_REG, 0x1, 0x1));
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/* ODPG Read enable/disable from BIST */
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CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num,
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ODPG_DATA_CONTROL_REG,
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(direction == OPER_READ) ?
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0x2 : 0, 0x2));
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CHECK_STATUS(ddr3_tip_load_pattern_to_odpg(dev_num, access_type, if_num,
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pattern, offset));
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CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num,
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ODPG_DATA_BUF_SIZE_REG,
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pattern_addr_length, MASK_ALL_BITS));
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tx_burst_size = (direction == OPER_WRITE) ?
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pattern_table[pattern].tx_burst_size : 0;
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delay_between_burst = (direction == OPER_WRITE) ? 2 : 0;
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rd_mode = (direction == OPER_WRITE) ? 1 : 0;
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CHECK_STATUS(ddr3_tip_configure_odpg
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(dev_num, access_type, if_num, direction,
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pattern_table[pattern].num_of_phases_tx, tx_burst_size,
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pattern_table[pattern].num_of_phases_rx,
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delay_between_burst,
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rd_mode, cs_num, addr_stress_jump, duration));
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CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num,
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ODPG_PATTERN_ADDR_OFFSET_REG,
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offset, MASK_ALL_BITS));
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if (oper_type == BIST_STOP) {
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CHECK_STATUS(ddr3_tip_bist_operation(dev_num, access_type,
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if_num, BIST_STOP));
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} else {
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CHECK_STATUS(ddr3_tip_bist_operation(dev_num, access_type,
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if_num, BIST_START));
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if (duration != DURATION_CONT) {
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/*
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* This pdelay is a WA, becuase polling fives "done"
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* also the odpg did nmot finish its task
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*/
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if (access_type == ACCESS_TYPE_MULTICAST) {
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start_if = 0;
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end_if = MAX_INTERFACE_NUM - 1;
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} else {
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start_if = if_num;
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end_if = if_num;
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}
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for (i = start_if; i <= end_if; i++) {
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VALIDATE_ACTIVE(tm->
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if_act_mask, i);
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for (poll_cnt = 0; poll_cnt < max_poll;
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poll_cnt++) {
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CHECK_STATUS(ddr3_tip_if_read
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(dev_num,
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ACCESS_TYPE_UNICAST,
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if_num, ODPG_BIST_DONE,
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read_data,
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MASK_ALL_BITS));
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val = read_data[i];
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if ((val & 0x1) == 0x0) {
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/*
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* In SOC type devices this bit
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* is self clear so, if it was
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* cleared all good
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*/
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break;
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}
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}
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if (poll_cnt >= max_poll) {
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DEBUG_TRAINING_BIST_ENGINE
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(DEBUG_LEVEL_ERROR,
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("Bist poll failure 2\n"));
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CHECK_STATUS(ddr3_tip_if_write
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(dev_num,
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ACCESS_TYPE_UNICAST,
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if_num,
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ODPG_DATA_CONTROL_REG, 0,
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MASK_ALL_BITS));
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return MV_FAIL;
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}
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}
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CHECK_STATUS(ddr3_tip_bist_operation
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(dev_num, access_type, if_num, BIST_STOP));
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}
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}
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CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num,
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ODPG_DATA_CONTROL_REG, 0,
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MASK_ALL_BITS));
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return MV_OK;
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}
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/*
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* BIST read result
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*/
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int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
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struct bist_result *pst_bist_result)
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{
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int ret;
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u32 read_data[MAX_INTERFACE_NUM];
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struct hws_topology_map *tm = ddr3_get_topology_map();
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if (IS_ACTIVE(tm->if_act_mask, if_id) == 0)
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return MV_NOT_SUPPORTED;
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DEBUG_TRAINING_BIST_ENGINE(DEBUG_LEVEL_TRACE,
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("ddr3_tip_bist_read_result if_id %d\n",
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if_id));
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ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id,
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ODPG_BIST_FAILED_DATA_HI_REG, read_data,
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MASK_ALL_BITS);
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if (ret != MV_OK)
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return ret;
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pst_bist_result->bist_fail_high = read_data[if_id];
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ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id,
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ODPG_BIST_FAILED_DATA_LOW_REG, read_data,
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MASK_ALL_BITS);
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if (ret != MV_OK)
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return ret;
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pst_bist_result->bist_fail_low = read_data[if_id];
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ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id,
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ODPG_BIST_LAST_FAIL_ADDR_REG, read_data,
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MASK_ALL_BITS);
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if (ret != MV_OK)
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return ret;
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pst_bist_result->bist_last_fail_addr = read_data[if_id];
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ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id,
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ODPG_BIST_DATA_ERROR_COUNTER_REG, read_data,
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MASK_ALL_BITS);
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if (ret != MV_OK)
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return ret;
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pst_bist_result->bist_error_cnt = read_data[if_id];
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return MV_OK;
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}
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/*
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* BIST flow - Activate & read result
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*/
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int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
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u32 cs_num)
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{
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int ret;
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u32 i = 0;
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u32 win_base;
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struct bist_result st_bist_result;
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struct hws_topology_map *tm = ddr3_get_topology_map();
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for (i = 0; i < MAX_INTERFACE_NUM; i++) {
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VALIDATE_ACTIVE(tm->if_act_mask, i);
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hws_ddr3_cs_base_adr_calc(i, cs_num, &win_base);
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ret = ddr3_tip_bist_activate(dev_num, pattern,
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ACCESS_TYPE_UNICAST,
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i, OPER_WRITE, STRESS_NONE,
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DURATION_SINGLE, BIST_START,
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bist_offset + win_base,
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cs_num, 15);
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if (ret != MV_OK) {
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printf("ddr3_tip_bist_activate failed (0x%x)\n", ret);
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return ret;
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}
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ret = ddr3_tip_bist_activate(dev_num, pattern,
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ACCESS_TYPE_UNICAST,
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i, OPER_READ, STRESS_NONE,
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DURATION_SINGLE, BIST_START,
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bist_offset + win_base,
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cs_num, 15);
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if (ret != MV_OK) {
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printf("ddr3_tip_bist_activate failed (0x%x)\n", ret);
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return ret;
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}
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ret = ddr3_tip_bist_read_result(dev_num, i, &st_bist_result);
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if (ret != MV_OK) {
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printf("ddr3_tip_bist_read_result failed\n");
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return ret;
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}
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result[i] = st_bist_result.bist_error_cnt;
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}
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return MV_OK;
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}
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/*
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* Set BIST Operation
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*/
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static int ddr3_tip_bist_operation(u32 dev_num,
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enum hws_access_type access_type,
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u32 if_id, enum hws_bist_operation oper_type)
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{
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if (oper_type == BIST_STOP) {
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CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
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ODPG_BIST_DONE, 1 << 8, 1 << 8));
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} else {
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CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
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ODPG_BIST_DONE, 1, 1));
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}
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return MV_OK;
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}
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/*
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* Print BIST result
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*/
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void ddr3_tip_print_bist_res(void)
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{
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u32 dev_num = 0;
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u32 i;
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struct bist_result st_bist_result[MAX_INTERFACE_NUM];
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int res;
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struct hws_topology_map *tm = ddr3_get_topology_map();
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for (i = 0; i < MAX_INTERFACE_NUM; i++) {
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if (IS_ACTIVE(tm->if_act_mask, i) == 0)
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continue;
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res = ddr3_tip_bist_read_result(dev_num, i, &st_bist_result[i]);
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if (res != MV_OK) {
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DEBUG_TRAINING_BIST_ENGINE(
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DEBUG_LEVEL_ERROR,
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("ddr3_tip_bist_read_result failed\n"));
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return;
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}
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}
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DEBUG_TRAINING_BIST_ENGINE(
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DEBUG_LEVEL_INFO,
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("interface | error_cnt | fail_low | fail_high | fail_addr\n"));
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for (i = 0; i < MAX_INTERFACE_NUM; i++) {
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if (IS_ACTIVE(tm->if_act_mask, i) ==
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0)
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continue;
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DEBUG_TRAINING_BIST_ENGINE(
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DEBUG_LEVEL_INFO,
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("%d | 0x%08x | 0x%08x | 0x%08x | 0x%08x\n",
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i, st_bist_result[i].bist_error_cnt,
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st_bist_result[i].bist_fail_low,
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st_bist_result[i].bist_fail_high,
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st_bist_result[i].bist_last_fail_addr));
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}
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}
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