135 lines
3.9 KiB
C
135 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* clock.h
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*
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* clock header
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*
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* Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/
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*/
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#ifndef _CLOCKS_H_
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#define _CLOCKS_H_
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#include <asm/arch/clocks_am33xx.h>
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#include <asm/arch/hardware.h>
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#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
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#include <asm/arch/clock_ti81xx.h>
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#endif
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#define LDELAY 1000000
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/*CM_<clock_domain>__CLKCTRL */
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#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
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#define CD_CLKCTRL_CLKTRCTRL_MASK 3
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#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
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#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
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#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
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/* CM_<clock_domain>_<module>_CLKCTRL */
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#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
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#define MODULE_CLKCTRL_MODULEMODE_MASK 3
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#define MODULE_CLKCTRL_IDLEST_SHIFT 16
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#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
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#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
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#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
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#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
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#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
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#define MODULE_CLKCTRL_IDLEST_IDLE 2
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#define MODULE_CLKCTRL_IDLEST_DISABLED 3
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/* CM_CLKMODE_DPLL */
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#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12
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#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12)
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#define CM_CLKMODE_DPLL_SSC_ACK_MASK (1 << 13)
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#define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
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#define CM_CLKMODE_DPLL_SSC_TYPE_MASK (1 << 15)
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#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
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#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
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#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
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#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
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#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
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#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
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#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
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#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
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#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
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#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
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#define CM_CLKMODE_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
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#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
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#define DPLL_EN_STOP 1
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#define DPLL_EN_MN_BYPASS 4
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#define DPLL_EN_LOW_POWER_BYPASS 5
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#define DPLL_EN_LOCK 7
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/* CM_IDLEST_DPLL fields */
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#define ST_DPLL_CLK_MASK 1
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/* CM_CLKSEL_DPLL */
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#define CM_CLKSEL_DPLL_M_SHIFT 8
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#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
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#define CM_CLKSEL_DPLL_N_SHIFT 0
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#define CM_CLKSEL_DPLL_N_MASK 0x7F
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struct dpll_params {
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u32 m;
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u32 n;
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s8 m2;
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s8 m3;
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s8 m4;
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s8 m5;
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s8 m6;
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};
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struct dpll_regs {
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u32 cm_clkmode_dpll;
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u32 cm_idlest_dpll;
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u32 cm_autoidle_dpll;
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u32 cm_clksel_dpll;
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u32 cm_div_m2_dpll;
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u32 cm_div_m3_dpll;
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u32 cm_div_m4_dpll;
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u32 cm_div_m5_dpll;
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u32 cm_div_m6_dpll;
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};
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extern const struct dpll_regs dpll_mpu_regs;
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extern const struct dpll_regs dpll_core_regs;
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extern const struct dpll_regs dpll_per_regs;
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extern const struct dpll_regs dpll_ddr_regs;
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extern const struct dpll_regs dpll_disp_regs;
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extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS];
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extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ];
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extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ];
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extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ];
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extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ];
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extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ];
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extern struct cm_wkuppll *const cmwkup;
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const struct dpll_params *get_dpll_mpu_params(void);
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const struct dpll_params *get_dpll_core_params(void);
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const struct dpll_params *get_dpll_per_params(void);
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const struct dpll_params *get_dpll_ddr_params(void);
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void scale_vcores(void);
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void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
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void prcm_init(void);
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void enable_basic_clocks(void);
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void rtc_only_update_board_type(u32 btype);
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u32 rtc_only_get_board_type(void);
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void rtc_only_prcm_init(void);
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void rtc_only_enable_basic_clocks(void);
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void do_enable_clocks(u32 *const *, u32 *const *, u8);
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void do_disable_clocks(u32 *const *, u32 *const *, u8);
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void set_mpu_spreadspectrum(int permille);
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#endif
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