144 lines
3.9 KiB
C
144 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Authors:
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* Aneesh V <aneesh@ti.com>
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*
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* Derived from OMAP3 work by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <x0khasim@ti.com>
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*/
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#ifndef _OMAP4_H_
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#define _OMAP4_H_
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
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#include <linux/sizes.h>
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/*
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* L4 Peripherals - L4 Wakeup and L4 Core now
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*/
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#define OMAP44XX_L4_CORE_BASE 0x4A000000
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#define OMAP44XX_L4_WKUP_BASE 0x4A300000
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#define OMAP44XX_L4_PER_BASE 0x48000000
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#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
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#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
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#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START
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#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END
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/* CONTROL_ID_CODE */
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#define CONTROL_ID_CODE 0x4A002204
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#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
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#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
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#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
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#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
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#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F
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#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
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#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
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#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F
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/* UART */
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#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
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#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
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#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
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/* General Purpose Timers */
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#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
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#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000)
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#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000)
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/* Watchdog Timer2 - MPU watchdog */
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#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
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/*
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* Hardware Register Details
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*/
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/* Watchdog Timer */
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#define WD_UNLOCK1 0xAAAA
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#define WD_UNLOCK2 0x5555
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/* GP Timer */
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#define TCLR_ST (0x1 << 0)
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#define TCLR_AR (0x1 << 1)
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#define TCLR_PRE (0x1 << 5)
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/* Control Module */
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#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
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#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
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#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
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#define CONTROL_EFUSE_2_OVERRIDE 0x99084000
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/* LPDDR2 IO regs */
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#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
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#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
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#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
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#define LPDDR2IO_GR10_WD_MASK (3 << 17)
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#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F
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/* CONTROL_EFUSE_2 */
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#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
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#define MMC1_PWRDNZ (1 << 26)
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#define MMC1_PBIASLITE_PWRDNZ (1 << 22)
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#define MMC1_PBIASLITE_VMODE (1 << 21)
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#ifndef __ASSEMBLY__
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struct s32ktimer {
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unsigned char res[0x10];
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unsigned int s32k_cr; /* 0x10 */
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};
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#define DEVICE_TYPE_SHIFT (0x8)
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#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
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#endif /* __ASSEMBLY__ */
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/*
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* Non-secure SRAM Addresses
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* Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
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* at 0x40304000(EMU base) so that our code works for both EMU and GP
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*/
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#define NON_SECURE_SRAM_START 0x40304000
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#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
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#define NON_SECURE_SRAM_IMG_END 0x4030C000
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#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
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/* base address for indirect vectors (internal boot mode) */
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#define SRAM_ROM_VECT_BASE 0x4030D000
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/* ABB settings */
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#define OMAP_ABB_SETTLING_TIME 50
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#define OMAP_ABB_CLOCK_CYCLES 16
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/* ABB tranxdone mask */
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#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)
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#define OMAP44XX_SAR_RAM_BASE 0x4a326000
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#define OMAP_REBOOT_REASON_OFFSET 0xA0C
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#define OMAP_REBOOT_REASON_SIZE 0x0F
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/* Boot parameters */
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#ifndef __ASSEMBLY__
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struct omap_boot_parameters {
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unsigned int boot_message;
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unsigned int boot_device_descriptor;
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unsigned char boot_device;
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unsigned char reset_reason;
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unsigned char ch_flags;
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};
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int omap_reboot_mode(char *mode, unsigned int length);
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int omap_reboot_mode_clear(void);
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int omap_reboot_mode_store(char *mode);
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#endif
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#endif
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